Static Timing Analysis

Project : PSoC5_EVB_LP
Build Time : 05/14/13 00:01:44
Device : CY8C5868LTI-LP038
Temperature : -40C - 85/125C
Vdda : 3.30
Vddd : 3.30
Vio0 : 3.30
Vio1 : 3.30
Vio2 : 3.30
Vio3 : 3.30
Voltage : 3.3
Vusb : 3.30
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 16.000 MHz 16.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 33.000 MHz 33.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 33.000 MHz 33.000 MHz 38.235 MHz
Clock_3 CyMASTER_CLK 1.375 MHz 1.435 MHz 34.903 MHz
UART_1_IntClock CyMASTER_CLK 1.833 MHz 1.833 MHz 41.085 MHz
Clock_2 CyMASTER_CLK 1.000 MHz 1.000 MHz 33.251 MHz
CyPLL_OUT CyPLL_OUT 33.000 MHz 33.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 1000ns(1 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\Timer1:CounterUDB:sC16:counterdp:u0\/z0 \Timer1:CounterUDB:sC16:counterdp:u1\/ci 33.251 MHz 30.074 969.926
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,1) 1 \Timer1:CounterUDB:sC16:counterdp:u0\ \Timer1:CounterUDB:sC16:counterdp:u0\/clock \Timer1:CounterUDB:sC16:counterdp:u0\/z0 2.320
Route 1 \Timer1:CounterUDB:sC16:counterdp:u0.z0__sig\ \Timer1:CounterUDB:sC16:counterdp:u0\/z0 \Timer1:CounterUDB:sC16:counterdp:u1\/z0i 0.000
datapathcell3 U(0,1) 1 \Timer1:CounterUDB:sC16:counterdp:u1\ \Timer1:CounterUDB:sC16:counterdp:u1\/z0i \Timer1:CounterUDB:sC16:counterdp:u1\/z0_comb 2.960
Route 1 \Timer1:CounterUDB:status_1\ \Timer1:CounterUDB:sC16:counterdp:u1\/z0_comb \Timer1:CounterUDB:reload\/main_1 4.058
macrocell46 U(1,1) 1 \Timer1:CounterUDB:reload\ \Timer1:CounterUDB:reload\/main_1 \Timer1:CounterUDB:reload\/q 3.350
Route 1 \Timer1:CounterUDB:reload\ \Timer1:CounterUDB:reload\/q \Timer1:CounterUDB:sC16:counterdp:u0\/cs_addr_0 2.586
datapathcell2 U(1,1) 1 \Timer1:CounterUDB:sC16:counterdp:u0\ \Timer1:CounterUDB:sC16:counterdp:u0\/cs_addr_0 \Timer1:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \Timer1:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Timer1:CounterUDB:sC16:counterdp:u0\/co_msb \Timer1:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell3 U(0,1) 1 \Timer1:CounterUDB:sC16:counterdp:u1\ SETUP 5.090
Clock Skew 0.000
\Timer2:CounterUDB:sC16:counterdp:u0\/z0 \Timer2:CounterUDB:sC16:counterdp:u1\/ci 33.629 MHz 29.736 970.264
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(1,2) 1 \Timer2:CounterUDB:sC16:counterdp:u0\ \Timer2:CounterUDB:sC16:counterdp:u0\/clock \Timer2:CounterUDB:sC16:counterdp:u0\/z0 2.320
Route 1 \Timer2:CounterUDB:sC16:counterdp:u0.z0__sig\ \Timer2:CounterUDB:sC16:counterdp:u0\/z0 \Timer2:CounterUDB:sC16:counterdp:u1\/z0i 0.000
datapathcell5 U(0,2) 1 \Timer2:CounterUDB:sC16:counterdp:u1\ \Timer2:CounterUDB:sC16:counterdp:u1\/z0i \Timer2:CounterUDB:sC16:counterdp:u1\/z0_comb 2.960
Route 1 \Timer2:CounterUDB:status_1\ \Timer2:CounterUDB:sC16:counterdp:u1\/z0_comb \Timer2:CounterUDB:reload\/main_1 3.504
macrocell53 U(0,2) 1 \Timer2:CounterUDB:reload\ \Timer2:CounterUDB:reload\/main_1 \Timer2:CounterUDB:reload\/q 3.350
Route 1 \Timer2:CounterUDB:reload\ \Timer2:CounterUDB:reload\/q \Timer2:CounterUDB:sC16:counterdp:u0\/cs_addr_0 2.802
datapathcell4 U(1,2) 1 \Timer2:CounterUDB:sC16:counterdp:u0\ \Timer2:CounterUDB:sC16:counterdp:u0\/cs_addr_0 \Timer2:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \Timer2:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Timer2:CounterUDB:sC16:counterdp:u0\/co_msb \Timer2:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell5 U(0,2) 1 \Timer2:CounterUDB:sC16:counterdp:u1\ SETUP 5.090
Clock Skew 0.000
\Timer1:CounterUDB:sC16:counterdp:u1\/z0_comb \Timer1:CounterUDB:sC16:counterdp:u1\/ci 34.911 MHz 28.644 971.356
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,1) 1 \Timer1:CounterUDB:sC16:counterdp:u1\ \Timer1:CounterUDB:sC16:counterdp:u1\/clock \Timer1:CounterUDB:sC16:counterdp:u1\/z0_comb 3.850
Route 1 \Timer1:CounterUDB:status_1\ \Timer1:CounterUDB:sC16:counterdp:u1\/z0_comb \Timer1:CounterUDB:reload\/main_1 4.058
macrocell46 U(1,1) 1 \Timer1:CounterUDB:reload\ \Timer1:CounterUDB:reload\/main_1 \Timer1:CounterUDB:reload\/q 3.350
Route 1 \Timer1:CounterUDB:reload\ \Timer1:CounterUDB:reload\/q \Timer1:CounterUDB:sC16:counterdp:u0\/cs_addr_0 2.586
datapathcell2 U(1,1) 1 \Timer1:CounterUDB:sC16:counterdp:u0\ \Timer1:CounterUDB:sC16:counterdp:u0\/cs_addr_0 \Timer1:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \Timer1:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Timer1:CounterUDB:sC16:counterdp:u0\/co_msb \Timer1:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell3 U(0,1) 1 \Timer1:CounterUDB:sC16:counterdp:u1\ SETUP 5.090
Clock Skew 0.000
\Timer2:CounterUDB:sC16:counterdp:u1\/z0_comb \Timer2:CounterUDB:sC16:counterdp:u1\/ci 35.328 MHz 28.306 971.694
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(0,2) 1 \Timer2:CounterUDB:sC16:counterdp:u1\ \Timer2:CounterUDB:sC16:counterdp:u1\/clock \Timer2:CounterUDB:sC16:counterdp:u1\/z0_comb 3.850
Route 1 \Timer2:CounterUDB:status_1\ \Timer2:CounterUDB:sC16:counterdp:u1\/z0_comb \Timer2:CounterUDB:reload\/main_1 3.504
macrocell53 U(0,2) 1 \Timer2:CounterUDB:reload\ \Timer2:CounterUDB:reload\/main_1 \Timer2:CounterUDB:reload\/q 3.350
Route 1 \Timer2:CounterUDB:reload\ \Timer2:CounterUDB:reload\/q \Timer2:CounterUDB:sC16:counterdp:u0\/cs_addr_0 2.802
datapathcell4 U(1,2) 1 \Timer2:CounterUDB:sC16:counterdp:u0\ \Timer2:CounterUDB:sC16:counterdp:u0\/cs_addr_0 \Timer2:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \Timer2:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Timer2:CounterUDB:sC16:counterdp:u0\/co_msb \Timer2:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell5 U(0,2) 1 \Timer2:CounterUDB:sC16:counterdp:u1\ SETUP 5.090
Clock Skew 0.000
Net_957/q \Timer2:CounterUDB:sC16:counterdp:u1\/ci 35.833 MHz 27.907 972.093
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(1,0) 1 Net_957 Net_957/clock_0 Net_957/q 1.250
Route 1 Net_957 Net_957/q \Timer2:CounterUDB:count_enable\/main_0 5.736
macrocell50 U(1,2) 1 \Timer2:CounterUDB:count_enable\ \Timer2:CounterUDB:count_enable\/main_0 \Timer2:CounterUDB:count_enable\/q 3.350
Route 1 \Timer2:CounterUDB:count_enable\ \Timer2:CounterUDB:count_enable\/q \Timer2:CounterUDB:sC16:counterdp:u0\/cs_addr_1 2.771
datapathcell4 U(1,2) 1 \Timer2:CounterUDB:sC16:counterdp:u0\ \Timer2:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \Timer2:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \Timer2:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Timer2:CounterUDB:sC16:counterdp:u0\/co_msb \Timer2:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell5 U(0,2) 1 \Timer2:CounterUDB:sC16:counterdp:u1\ SETUP 5.090
Clock Skew 0.000
\Timer1:CounterUDB:sC16:counterdp:u0\/z0 \Timer1:CounterUDB:sC16:counterdp:u1\/cs_addr_0 37.316 MHz 26.798 973.202
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,1) 1 \Timer1:CounterUDB:sC16:counterdp:u0\ \Timer1:CounterUDB:sC16:counterdp:u0\/clock \Timer1:CounterUDB:sC16:counterdp:u0\/z0 2.320
Route 1 \Timer1:CounterUDB:sC16:counterdp:u0.z0__sig\ \Timer1:CounterUDB:sC16:counterdp:u0\/z0 \Timer1:CounterUDB:sC16:counterdp:u1\/z0i 0.000
datapathcell3 U(0,1) 1 \Timer1:CounterUDB:sC16:counterdp:u1\ \Timer1:CounterUDB:sC16:counterdp:u1\/z0i \Timer1:CounterUDB:sC16:counterdp:u1\/z0_comb 2.960
Route 1 \Timer1:CounterUDB:status_1\ \Timer1:CounterUDB:sC16:counterdp:u1\/z0_comb \Timer1:CounterUDB:reload\/main_1 4.058
macrocell46 U(1,1) 1 \Timer1:CounterUDB:reload\ \Timer1:CounterUDB:reload\/main_1 \Timer1:CounterUDB:reload\/q 3.350
Route 1 \Timer1:CounterUDB:reload\ \Timer1:CounterUDB:reload\/q \Timer1:CounterUDB:sC16:counterdp:u1\/cs_addr_0 2.590
datapathcell3 U(0,1) 1 \Timer1:CounterUDB:sC16:counterdp:u1\ SETUP 11.520
Clock Skew 0.000
\Timer1:CounterUDB:sC16:counterdp:u0\/z0 \Timer1:CounterUDB:sC16:counterdp:u0\/cs_addr_0 37.322 MHz 26.794 973.206
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,1) 1 \Timer1:CounterUDB:sC16:counterdp:u0\ \Timer1:CounterUDB:sC16:counterdp:u0\/clock \Timer1:CounterUDB:sC16:counterdp:u0\/z0 2.320
Route 1 \Timer1:CounterUDB:sC16:counterdp:u0.z0__sig\ \Timer1:CounterUDB:sC16:counterdp:u0\/z0 \Timer1:CounterUDB:sC16:counterdp:u1\/z0i 0.000
datapathcell3 U(0,1) 1 \Timer1:CounterUDB:sC16:counterdp:u1\ \Timer1:CounterUDB:sC16:counterdp:u1\/z0i \Timer1:CounterUDB:sC16:counterdp:u1\/z0_comb 2.960
Route 1 \Timer1:CounterUDB:status_1\ \Timer1:CounterUDB:sC16:counterdp:u1\/z0_comb \Timer1:CounterUDB:reload\/main_1 4.058
macrocell46 U(1,1) 1 \Timer1:CounterUDB:reload\ \Timer1:CounterUDB:reload\/main_1 \Timer1:CounterUDB:reload\/q 3.350
Route 1 \Timer1:CounterUDB:reload\ \Timer1:CounterUDB:reload\/q \Timer1:CounterUDB:sC16:counterdp:u0\/cs_addr_0 2.586
datapathcell2 U(1,1) 1 \Timer1:CounterUDB:sC16:counterdp:u0\ SETUP 11.520
Clock Skew 0.000
\Timer2:CounterUDB:sC16:counterdp:u0\/z0 \Timer2:CounterUDB:sC16:counterdp:u0\/cs_addr_0 37.799 MHz 26.456 973.544
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(1,2) 1 \Timer2:CounterUDB:sC16:counterdp:u0\ \Timer2:CounterUDB:sC16:counterdp:u0\/clock \Timer2:CounterUDB:sC16:counterdp:u0\/z0 2.320
Route 1 \Timer2:CounterUDB:sC16:counterdp:u0.z0__sig\ \Timer2:CounterUDB:sC16:counterdp:u0\/z0 \Timer2:CounterUDB:sC16:counterdp:u1\/z0i 0.000
datapathcell5 U(0,2) 1 \Timer2:CounterUDB:sC16:counterdp:u1\ \Timer2:CounterUDB:sC16:counterdp:u1\/z0i \Timer2:CounterUDB:sC16:counterdp:u1\/z0_comb 2.960
Route 1 \Timer2:CounterUDB:status_1\ \Timer2:CounterUDB:sC16:counterdp:u1\/z0_comb \Timer2:CounterUDB:reload\/main_1 3.504
macrocell53 U(0,2) 1 \Timer2:CounterUDB:reload\ \Timer2:CounterUDB:reload\/main_1 \Timer2:CounterUDB:reload\/q 3.350
Route 1 \Timer2:CounterUDB:reload\ \Timer2:CounterUDB:reload\/q \Timer2:CounterUDB:sC16:counterdp:u0\/cs_addr_0 2.802
datapathcell4 U(1,2) 1 \Timer2:CounterUDB:sC16:counterdp:u0\ SETUP 11.520
Clock Skew 0.000
\Timer2:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer2:CounterUDB:sC16:counterdp:u1\/ci 37.817 MHz 26.443 973.557
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(1,3) 1 \Timer2:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer2:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer2:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.580
Route 1 \Timer2:CounterUDB:control_7\ \Timer2:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer2:CounterUDB:count_enable\/main_1 2.942
macrocell50 U(1,2) 1 \Timer2:CounterUDB:count_enable\ \Timer2:CounterUDB:count_enable\/main_1 \Timer2:CounterUDB:count_enable\/q 3.350
Route 1 \Timer2:CounterUDB:count_enable\ \Timer2:CounterUDB:count_enable\/q \Timer2:CounterUDB:sC16:counterdp:u0\/cs_addr_1 2.771
datapathcell4 U(1,2) 1 \Timer2:CounterUDB:sC16:counterdp:u0\ \Timer2:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \Timer2:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \Timer2:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Timer2:CounterUDB:sC16:counterdp:u0\/co_msb \Timer2:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell5 U(0,2) 1 \Timer2:CounterUDB:sC16:counterdp:u1\ SETUP 5.090
Clock Skew 0.000
\Timer2:CounterUDB:sC16:counterdp:u0\/z0 \Timer2:CounterUDB:sC16:counterdp:u1\/cs_addr_0 37.840 MHz 26.427 973.573
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(1,2) 1 \Timer2:CounterUDB:sC16:counterdp:u0\ \Timer2:CounterUDB:sC16:counterdp:u0\/clock \Timer2:CounterUDB:sC16:counterdp:u0\/z0 2.320
Route 1 \Timer2:CounterUDB:sC16:counterdp:u0.z0__sig\ \Timer2:CounterUDB:sC16:counterdp:u0\/z0 \Timer2:CounterUDB:sC16:counterdp:u1\/z0i 0.000
datapathcell5 U(0,2) 1 \Timer2:CounterUDB:sC16:counterdp:u1\ \Timer2:CounterUDB:sC16:counterdp:u1\/z0i \Timer2:CounterUDB:sC16:counterdp:u1\/z0_comb 2.960
Route 1 \Timer2:CounterUDB:status_1\ \Timer2:CounterUDB:sC16:counterdp:u1\/z0_comb \Timer2:CounterUDB:reload\/main_1 3.504
macrocell53 U(0,2) 1 \Timer2:CounterUDB:reload\ \Timer2:CounterUDB:reload\/main_1 \Timer2:CounterUDB:reload\/q 3.350
Route 1 \Timer2:CounterUDB:reload\ \Timer2:CounterUDB:reload\/q \Timer2:CounterUDB:sC16:counterdp:u1\/cs_addr_0 2.773
datapathcell5 U(0,2) 1 \Timer2:CounterUDB:sC16:counterdp:u1\ SETUP 11.520
Clock Skew 0.000
Path Delay Requirement : 696.97ns(1.43478 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\SD_SPIM:BSPIM:state_2\/q \SD_SPIM:BSPIM:TxStsReg\/status_0 34.903 MHz 28.651 668.319
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell39 U(2,2) 1 \SD_SPIM:BSPIM:state_2\ \SD_SPIM:BSPIM:state_2\/clock_0 \SD_SPIM:BSPIM:state_2\/q 1.250
Route 1 \SD_SPIM:BSPIM:state_2\ \SD_SPIM:BSPIM:state_2\/q \SD_SPIM:BSPIM:tx_status_0\/main_0 14.311
macrocell40 U(1,4) 1 \SD_SPIM:BSPIM:tx_status_0\ \SD_SPIM:BSPIM:tx_status_0\/main_0 \SD_SPIM:BSPIM:tx_status_0\/q 3.350
Route 1 \SD_SPIM:BSPIM:tx_status_0\ \SD_SPIM:BSPIM:tx_status_0\/q \SD_SPIM:BSPIM:TxStsReg\/status_0 8.170
statusicell2 U(1,0) 1 \SD_SPIM:BSPIM:TxStsReg\ SETUP 1.570
Clock Skew 0.000
\SD_SPIM:BSPIM:state_1\/q \SD_SPIM:BSPIM:TxStsReg\/status_0 39.417 MHz 25.370 671.600
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell38 U(2,0) 1 \SD_SPIM:BSPIM:state_1\ \SD_SPIM:BSPIM:state_1\/clock_0 \SD_SPIM:BSPIM:state_1\/q 1.250
Route 1 \SD_SPIM:BSPIM:state_1\ \SD_SPIM:BSPIM:state_1\/q \SD_SPIM:BSPIM:tx_status_0\/main_1 11.030
macrocell40 U(1,4) 1 \SD_SPIM:BSPIM:tx_status_0\ \SD_SPIM:BSPIM:tx_status_0\/main_1 \SD_SPIM:BSPIM:tx_status_0\/q 3.350
Route 1 \SD_SPIM:BSPIM:tx_status_0\ \SD_SPIM:BSPIM:tx_status_0\/q \SD_SPIM:BSPIM:TxStsReg\/status_0 8.170
statusicell2 U(1,0) 1 \SD_SPIM:BSPIM:TxStsReg\ SETUP 1.570
Clock Skew 0.000
\SD_SPIM:BSPIM:state_0\/q \SD_SPIM:BSPIM:TxStsReg\/status_0 41.901 MHz 23.866 673.104
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell37 U(2,2) 1 \SD_SPIM:BSPIM:state_0\ \SD_SPIM:BSPIM:state_0\/clock_0 \SD_SPIM:BSPIM:state_0\/q 1.250
Route 1 \SD_SPIM:BSPIM:state_0\ \SD_SPIM:BSPIM:state_0\/q \SD_SPIM:BSPIM:tx_status_0\/main_2 9.526
macrocell40 U(1,4) 1 \SD_SPIM:BSPIM:tx_status_0\ \SD_SPIM:BSPIM:tx_status_0\/main_2 \SD_SPIM:BSPIM:tx_status_0\/q 3.350
Route 1 \SD_SPIM:BSPIM:tx_status_0\ \SD_SPIM:BSPIM:tx_status_0\/q \SD_SPIM:BSPIM:TxStsReg\/status_0 8.170
statusicell2 U(1,0) 1 \SD_SPIM:BSPIM:TxStsReg\ SETUP 1.570
Clock Skew 0.000
\SD_SPIM:BSPIM:state_2\/q \SD_SPIM:BSPIM:mosi_hs_reg\/main_0 43.683 MHz 22.892 674.078
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell39 U(2,2) 1 \SD_SPIM:BSPIM:state_2\ \SD_SPIM:BSPIM:state_2\/clock_0 \SD_SPIM:BSPIM:state_2\/q 1.250
Route 1 \SD_SPIM:BSPIM:state_2\ \SD_SPIM:BSPIM:state_2\/q \SD_SPIM:BSPIM:mosi_hs_reg\/main_0 18.132
macrocell32 U(3,4) 1 \SD_SPIM:BSPIM:mosi_hs_reg\ SETUP 3.510
Clock Skew 0.000
\SD_SPIM:BSPIM:sR8:Dp:u0\/so_comb \SD_SPIM:BSPIM:mosi_pre_reg\/main_0 47.881 MHz 20.885 676.085
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,1) 1 \SD_SPIM:BSPIM:sR8:Dp:u0\ \SD_SPIM:BSPIM:sR8:Dp:u0\/clock \SD_SPIM:BSPIM:sR8:Dp:u0\/so_comb 8.300
Route 1 \SD_SPIM:BSPIM:mosi_from_dp\ \SD_SPIM:BSPIM:sR8:Dp:u0\/so_comb \SD_SPIM:BSPIM:mosi_pre_reg_split\/main_3 3.427
macrocell34 U(2,1) 1 \SD_SPIM:BSPIM:mosi_pre_reg_split\ \SD_SPIM:BSPIM:mosi_pre_reg_split\/main_3 \SD_SPIM:BSPIM:mosi_pre_reg_split\/q 3.350
Route 1 \SD_SPIM:BSPIM:mosi_pre_reg_split\ \SD_SPIM:BSPIM:mosi_pre_reg_split\/q \SD_SPIM:BSPIM:mosi_pre_reg\/main_0 2.298
macrocell33 U(2,1) 1 \SD_SPIM:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\SD_SPIM:BSPIM:sR8:Dp:u0\/so_comb \SD_SPIM:BSPIM:mosi_pre_reg\/main_1 47.923 MHz 20.867 676.103
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,1) 1 \SD_SPIM:BSPIM:sR8:Dp:u0\ \SD_SPIM:BSPIM:sR8:Dp:u0\/clock \SD_SPIM:BSPIM:sR8:Dp:u0\/so_comb 8.300
Route 1 \SD_SPIM:BSPIM:mosi_from_dp\ \SD_SPIM:BSPIM:sR8:Dp:u0\/so_comb \SD_SPIM:BSPIM:mosi_pre_reg_split_1\/main_3 3.416
macrocell35 U(2,1) 1 \SD_SPIM:BSPIM:mosi_pre_reg_split_1\ \SD_SPIM:BSPIM:mosi_pre_reg_split_1\/main_3 \SD_SPIM:BSPIM:mosi_pre_reg_split_1\/q 3.350
Route 1 \SD_SPIM:BSPIM:mosi_pre_reg_split_1\ \SD_SPIM:BSPIM:mosi_pre_reg_split_1\/q \SD_SPIM:BSPIM:mosi_pre_reg\/main_1 2.291
macrocell33 U(2,1) 1 \SD_SPIM:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\SD_SPIM:BSPIM:BitCounter\/count_0 \SD_SPIM:BSPIM:TxStsReg\/status_3 48.600 MHz 20.576 676.394
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,1) 1 \SD_SPIM:BSPIM:BitCounter\ \SD_SPIM:BSPIM:BitCounter\/clock \SD_SPIM:BSPIM:BitCounter\/count_0 2.110
Route 1 \SD_SPIM:BSPIM:count_0\ \SD_SPIM:BSPIM:BitCounter\/count_0 \SD_SPIM:BSPIM:load_rx_data\/main_4 5.651
macrocell30 U(2,2) 1 \SD_SPIM:BSPIM:load_rx_data\ \SD_SPIM:BSPIM:load_rx_data\/main_4 \SD_SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SD_SPIM:BSPIM:load_rx_data\ \SD_SPIM:BSPIM:load_rx_data\/q \SD_SPIM:BSPIM:TxStsReg\/status_3 7.895
statusicell2 U(1,0) 1 \SD_SPIM:BSPIM:TxStsReg\ SETUP 1.570
Clock Skew 0.000
\SD_SPIM:BSPIM:BitCounter\/count_4 \SD_SPIM:BSPIM:TxStsReg\/status_3 50.292 MHz 19.884 677.086
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,1) 1 \SD_SPIM:BSPIM:BitCounter\ \SD_SPIM:BSPIM:BitCounter\/clock \SD_SPIM:BSPIM:BitCounter\/count_4 2.110
Route 1 \SD_SPIM:BSPIM:count_4\ \SD_SPIM:BSPIM:BitCounter\/count_4 \SD_SPIM:BSPIM:load_rx_data\/main_0 4.959
macrocell30 U(2,2) 1 \SD_SPIM:BSPIM:load_rx_data\ \SD_SPIM:BSPIM:load_rx_data\/main_0 \SD_SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SD_SPIM:BSPIM:load_rx_data\ \SD_SPIM:BSPIM:load_rx_data\/q \SD_SPIM:BSPIM:TxStsReg\/status_3 7.895
statusicell2 U(1,0) 1 \SD_SPIM:BSPIM:TxStsReg\ SETUP 1.570
Clock Skew 0.000
\SD_SPIM:BSPIM:BitCounter\/count_3 \SD_SPIM:BSPIM:TxStsReg\/status_3 50.393 MHz 19.844 677.126
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,1) 1 \SD_SPIM:BSPIM:BitCounter\ \SD_SPIM:BSPIM:BitCounter\/clock \SD_SPIM:BSPIM:BitCounter\/count_3 2.110
Route 1 \SD_SPIM:BSPIM:count_3\ \SD_SPIM:BSPIM:BitCounter\/count_3 \SD_SPIM:BSPIM:load_rx_data\/main_1 4.919
macrocell30 U(2,2) 1 \SD_SPIM:BSPIM:load_rx_data\ \SD_SPIM:BSPIM:load_rx_data\/main_1 \SD_SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SD_SPIM:BSPIM:load_rx_data\ \SD_SPIM:BSPIM:load_rx_data\/q \SD_SPIM:BSPIM:TxStsReg\/status_3 7.895
statusicell2 U(1,0) 1 \SD_SPIM:BSPIM:TxStsReg\ SETUP 1.570
Clock Skew 0.000
\SD_SPIM:BSPIM:state_2\/q \SD_SPIM:BSPIM:mosi_pre_reg\/main_0 51.300 MHz 19.493 677.477
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell39 U(2,2) 1 \SD_SPIM:BSPIM:state_2\ \SD_SPIM:BSPIM:state_2\/clock_0 \SD_SPIM:BSPIM:state_2\/q 1.250
Route 1 \SD_SPIM:BSPIM:state_2\ \SD_SPIM:BSPIM:state_2\/q \SD_SPIM:BSPIM:mosi_pre_reg_split\/main_0 9.085
macrocell34 U(2,1) 1 \SD_SPIM:BSPIM:mosi_pre_reg_split\ \SD_SPIM:BSPIM:mosi_pre_reg_split\/main_0 \SD_SPIM:BSPIM:mosi_pre_reg_split\/q 3.350
Route 1 \SD_SPIM:BSPIM:mosi_pre_reg_split\ \SD_SPIM:BSPIM:mosi_pre_reg_split\/q \SD_SPIM:BSPIM:mosi_pre_reg\/main_0 2.298
macrocell33 U(2,1) 1 \SD_SPIM:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 30.303ns(33 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
\Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:sC16:counterdp:u1\/ci 38.235 MHz 26.154 4.149
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(0,2) 1 \Timer2_Reset:Sync:ctrl_reg\ \Timer2_Reset:Sync:ctrl_reg\/busclk \Timer2_Reset:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_928 \Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:reload\/main_0 2.622
macrocell53 U(0,2) 1 \Timer2:CounterUDB:reload\ \Timer2:CounterUDB:reload\/main_0 \Timer2:CounterUDB:reload\/q 3.350
Route 1 \Timer2:CounterUDB:reload\ \Timer2:CounterUDB:reload\/q \Timer2:CounterUDB:sC16:counterdp:u0\/cs_addr_0 2.802
datapathcell4 U(1,2) 1 \Timer2:CounterUDB:sC16:counterdp:u0\ \Timer2:CounterUDB:sC16:counterdp:u0\/cs_addr_0 \Timer2:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \Timer2:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Timer2:CounterUDB:sC16:counterdp:u0\/co_msb \Timer2:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell5 U(0,2) 1 \Timer2:CounterUDB:sC16:counterdp:u1\ SETUP 5.090
Clock Skew 0.000
\Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:sC16:counterdp:u1\/ci 38.275 MHz 26.127 4.176
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(0,1) 1 \Timer1_Reset:Sync:ctrl_reg\ \Timer1_Reset:Sync:ctrl_reg\/busclk \Timer1_Reset:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_917 \Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:reload\/main_0 2.811
macrocell46 U(1,1) 1 \Timer1:CounterUDB:reload\ \Timer1:CounterUDB:reload\/main_0 \Timer1:CounterUDB:reload\/q 3.350
Route 1 \Timer1:CounterUDB:reload\ \Timer1:CounterUDB:reload\/q \Timer1:CounterUDB:sC16:counterdp:u0\/cs_addr_0 2.586
datapathcell2 U(1,1) 1 \Timer1:CounterUDB:sC16:counterdp:u0\ \Timer1:CounterUDB:sC16:counterdp:u0\/cs_addr_0 \Timer1:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \Timer1:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Timer1:CounterUDB:sC16:counterdp:u0\/co_msb \Timer1:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell3 U(0,1) 1 \Timer1:CounterUDB:sC16:counterdp:u1\ SETUP 5.090
Clock Skew 0.000
\Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:sC16:counterdp:u0\/cs_addr_0 43.718 MHz 22.874 7.429
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(0,2) 1 \Timer2_Reset:Sync:ctrl_reg\ \Timer2_Reset:Sync:ctrl_reg\/busclk \Timer2_Reset:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_928 \Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:reload\/main_0 2.622
macrocell53 U(0,2) 1 \Timer2:CounterUDB:reload\ \Timer2:CounterUDB:reload\/main_0 \Timer2:CounterUDB:reload\/q 3.350
Route 1 \Timer2:CounterUDB:reload\ \Timer2:CounterUDB:reload\/q \Timer2:CounterUDB:sC16:counterdp:u0\/cs_addr_0 2.802
datapathcell4 U(1,2) 1 \Timer2:CounterUDB:sC16:counterdp:u0\ SETUP 11.520
Clock Skew 0.000
\Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:sC16:counterdp:u1\/cs_addr_0 43.762 MHz 22.851 7.452
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(0,1) 1 \Timer1_Reset:Sync:ctrl_reg\ \Timer1_Reset:Sync:ctrl_reg\/busclk \Timer1_Reset:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_917 \Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:reload\/main_0 2.811
macrocell46 U(1,1) 1 \Timer1:CounterUDB:reload\ \Timer1:CounterUDB:reload\/main_0 \Timer1:CounterUDB:reload\/q 3.350
Route 1 \Timer1:CounterUDB:reload\ \Timer1:CounterUDB:reload\/q \Timer1:CounterUDB:sC16:counterdp:u1\/cs_addr_0 2.590
datapathcell3 U(0,1) 1 \Timer1:CounterUDB:sC16:counterdp:u1\ SETUP 11.520
Clock Skew 0.000
\Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:sC16:counterdp:u0\/cs_addr_0 43.769 MHz 22.847 7.456
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(0,1) 1 \Timer1_Reset:Sync:ctrl_reg\ \Timer1_Reset:Sync:ctrl_reg\/busclk \Timer1_Reset:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_917 \Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:reload\/main_0 2.811
macrocell46 U(1,1) 1 \Timer1:CounterUDB:reload\ \Timer1:CounterUDB:reload\/main_0 \Timer1:CounterUDB:reload\/q 3.350
Route 1 \Timer1:CounterUDB:reload\ \Timer1:CounterUDB:reload\/q \Timer1:CounterUDB:sC16:counterdp:u0\/cs_addr_0 2.586
datapathcell2 U(1,1) 1 \Timer1:CounterUDB:sC16:counterdp:u0\ SETUP 11.520
Clock Skew 0.000
\Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:sC16:counterdp:u1\/cs_addr_0 43.773 MHz 22.845 7.458
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(0,2) 1 \Timer2_Reset:Sync:ctrl_reg\ \Timer2_Reset:Sync:ctrl_reg\/busclk \Timer2_Reset:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_928 \Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:reload\/main_0 2.622
macrocell53 U(0,2) 1 \Timer2:CounterUDB:reload\ \Timer2:CounterUDB:reload\/main_0 \Timer2:CounterUDB:reload\/q 3.350
Route 1 \Timer2:CounterUDB:reload\ \Timer2:CounterUDB:reload\/q \Timer2:CounterUDB:sC16:counterdp:u1\/cs_addr_0 2.773
datapathcell5 U(0,2) 1 \Timer2:CounterUDB:sC16:counterdp:u1\ SETUP 11.520
Clock Skew 0.000
\Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:disable_run_i\/main_0 112.347 MHz 8.901 21.402
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(0,1) 1 \Timer1_Reset:Sync:ctrl_reg\ \Timer1_Reset:Sync:ctrl_reg\/busclk \Timer1_Reset:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_917 \Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:disable_run_i\/main_0 2.811
macrocell44 U(1,1) 1 \Timer1:CounterUDB:disable_run_i\ SETUP 3.510
Clock Skew 0.000
\Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:disable_run_i\/main_0 114.784 MHz 8.712 21.591
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(0,2) 1 \Timer2_Reset:Sync:ctrl_reg\ \Timer2_Reset:Sync:ctrl_reg\/busclk \Timer2_Reset:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_928 \Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:disable_run_i\/main_0 2.622
macrocell51 U(0,2) 1 \Timer2:CounterUDB:disable_run_i\ SETUP 3.510
Clock Skew 0.000
\Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:sSTSReg:rstSts:stsreg\/reset 186.359 MHz 5.366 24.937
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(0,1) 1 \Timer1_Reset:Sync:ctrl_reg\ \Timer1_Reset:Sync:ctrl_reg\/busclk \Timer1_Reset:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_917 \Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:sSTSReg:rstSts:stsreg\/reset 2.786
statusicell3 U(0,1) 1 \Timer1:CounterUDB:sSTSReg:rstSts:stsreg\ RECOVERY -0.000
Clock Skew 0.000
\Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:sSTSReg:rstSts:stsreg\/reset 193.274 MHz 5.174 25.129
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(0,2) 1 \Timer2_Reset:Sync:ctrl_reg\ \Timer2_Reset:Sync:ctrl_reg\/busclk \Timer2_Reset:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_928 \Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:sSTSReg:rstSts:stsreg\/reset 2.594
statusicell4 U(0,2) 1 \Timer2:CounterUDB:sSTSReg:rstSts:stsreg\ RECOVERY -0.000
Clock Skew 0.000
Path Delay Requirement : 30.303ns(33 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
SD_MISO(0)/fb \SD_SPIM:BSPIM:sR8:Dp:u0\/route_si 66.653 MHz 15.003 15.300
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell7 P12[7] 1 SD_MISO(0) SD_MISO(0)/in_clock SD_MISO(0)/fb 1.743
Route 1 Net_34 SD_MISO(0)/fb \SD_SPIM:BSPIM:sR8:Dp:u0\/route_si 6.480
datapathcell1 U(2,1) 1 \SD_SPIM:BSPIM:sR8:Dp:u0\ SETUP 6.780
Clock Skew 0.000
Path Delay Requirement : 30.303ns(33 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx_1(0)/fb \UART_1:BUART:sRX:RxShifter:u0\/route_si 51.664 MHz 19.356 10.947
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.828
Route 1 Net_127 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_1 6.661
macrocell67 U(0,4) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.307
datapathcell6 U(0,4) 1 \UART_1:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_6 61.713 MHz 16.204 14.099
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.828
Route 1 Net_127 Rx_1(0)/fb \UART_1:BUART:pollcount_1_split\/main_6 5.231
macrocell60 U(1,5) 1 \UART_1:BUART:pollcount_1_split\ \UART_1:BUART:pollcount_1_split\/main_6 \UART_1:BUART:pollcount_1_split\/q 3.350
Route 1 \UART_1:BUART:pollcount_1_split\ \UART_1:BUART:pollcount_1_split\/q \UART_1:BUART:pollcount_1\/main_6 2.285
macrocell59 U(1,5) 1 \UART_1:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 73.362 MHz 13.631 16.672
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.828
Route 1 Net_127 Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 8.293
macrocell69 U(0,3) 1 \UART_1:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 76.581 MHz 13.058 17.245
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.828
Route 1 Net_127 Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 7.720
macrocell65 U(2,4) 1 \UART_1:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 83.340 MHz 11.999 18.304
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.828
Route 1 Net_127 Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 6.661
macrocell68 U(0,4) 1 \UART_1:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 83.340 MHz 11.999 18.304
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.828
Route 1 Net_127 Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 6.661
macrocell72 U(0,4) 1 \UART_1:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_5 94.349 MHz 10.599 19.704
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.828
Route 1 Net_127 Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_5 5.261
macrocell58 U(1,5) 1 \UART_1:BUART:pollcount_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_5 94.349 MHz 10.599 19.704
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.828
Route 1 Net_127 Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_5 5.261
macrocell59 U(1,5) 1 \UART_1:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 545.455ns(1.83333 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 41.085 MHz 24.340 521.115
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell8 U(2,4) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb 5.680
Route 1 \UART_1:BUART:tx_bitclk_dp\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART_1:BUART:tx_bitclk_enable_pre\/main_0 6.708
macrocell76 U(1,4) 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:tx_bitclk_enable_pre\/main_0 \UART_1:BUART:tx_bitclk_enable_pre\/q 3.350
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:tx_bitclk_enable_pre\/q \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 2.312
datapathcell7 U(1,4) 1 \UART_1:BUART:sTX:TxShifter:u0\ SETUP 6.290
Clock Skew 0.000
\UART_1:BUART:tx_state_1\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 42.810 MHz 23.359 522.096
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell78 U(2,4) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 \UART_1:BUART:tx_state_1\/q 1.250
Route 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q \UART_1:BUART:counter_load_not\/main_0 4.924
macrocell57 U(3,4) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_0 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.315
datapathcell8 U(2,4) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_1:BUART:tx_state_0\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 43.324 MHz 23.082 522.373
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell77 U(2,4) 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/clock_0 \UART_1:BUART:tx_state_0\/q 1.250
Route 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/q \UART_1:BUART:counter_load_not\/main_1 4.647
macrocell57 U(3,4) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_1 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.315
datapathcell8 U(2,4) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_1:BUART:tx_bitclk\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 43.545 MHz 22.965 522.490
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell75 U(2,4) 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/clock_0 \UART_1:BUART:tx_bitclk\/q 1.250
Route 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/q \UART_1:BUART:counter_load_not\/main_3 4.530
macrocell57 U(3,4) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_3 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.315
datapathcell8 U(2,4) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 44.022 MHz 22.716 522.739
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell79 U(2,4) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 1.250
Route 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:counter_load_not\/main_2 4.281
macrocell57 U(3,4) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_2 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.315
datapathcell8 U(2,4) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:sTX:TxSts\/status_0 50.785 MHz 19.691 525.764
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell7 U(1,4) 1 \UART_1:BUART:sTX:TxShifter:u0\ \UART_1:BUART:sTX:TxShifter:u0\/clock \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \UART_1:BUART:tx_fifo_empty\ \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:tx_status_0\/main_2 7.196
macrocell80 U(3,4) 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/main_2 \UART_1:BUART:tx_status_0\/q 3.350
Route 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/q \UART_1:BUART:sTX:TxSts\/status_0 2.295
statusicell6 U(3,4) 1 \UART_1:BUART:sTX:TxSts\ SETUP 1.570
Clock Skew 0.000
\UART_1:BUART:rx_state_2\/q \UART_1:BUART:sRX:RxBitCounter\/load 58.238 MHz 17.171 528.284
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell69 U(0,3) 1 \UART_1:BUART:rx_state_2\ \UART_1:BUART:rx_state_2\/clock_0 \UART_1:BUART:rx_state_2\/q 1.250
Route 1 \UART_1:BUART:rx_state_2\ \UART_1:BUART:rx_state_2\/q \UART_1:BUART:rx_counter_load\/main_3 6.039
macrocell64 U(0,5) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_3 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.312
count7cell U(0,5) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 4.220
Clock Skew 0.000
\UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:tx_state_0\/main_2 59.319 MHz 16.858 528.597
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell7 U(1,4) 1 \UART_1:BUART:sTX:TxShifter:u0\ \UART_1:BUART:sTX:TxShifter:u0\/clock \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \UART_1:BUART:tx_fifo_empty\ \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:tx_state_0\/main_2 8.068
macrocell77 U(2,4) 1 \UART_1:BUART:tx_state_0\ SETUP 3.510
Clock Skew 0.000
\UART_1:BUART:tx_state_1\/q \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_2 63.403 MHz 15.772 529.683
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell78 U(2,4) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 \UART_1:BUART:tx_state_1\/q 1.250
Route 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_2 8.232
datapathcell7 U(1,4) 1 \UART_1:BUART:sTX:TxShifter:u0\ SETUP 6.290
Clock Skew 0.000
\UART_1:BUART:pollcount_1\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 63.792 MHz 15.676 529.779
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell59 U(1,5) 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/clock_0 \UART_1:BUART:pollcount_1\/q 1.250
Route 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/q \UART_1:BUART:rx_postpoll\/main_0 3.559
macrocell67 U(0,4) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_0 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.307
datapathcell6 U(0,4) 1 \UART_1:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\Timer1:CounterUDB:sC16:counterdp:u0\/co_msb \Timer1:CounterUDB:sC16:counterdp:u1\/ci 3.210
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,1) 1 \Timer1:CounterUDB:sC16:counterdp:u0\ \Timer1:CounterUDB:sC16:counterdp:u0\/clock \Timer1:CounterUDB:sC16:counterdp:u0\/co_msb 3.210
Route 1 \Timer1:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Timer1:CounterUDB:sC16:counterdp:u0\/co_msb \Timer1:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell3 U(0,1) 1 \Timer1:CounterUDB:sC16:counterdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer2:CounterUDB:sC16:counterdp:u0\/co_msb \Timer2:CounterUDB:sC16:counterdp:u1\/ci 3.210
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(1,2) 1 \Timer2:CounterUDB:sC16:counterdp:u0\ \Timer2:CounterUDB:sC16:counterdp:u0\/clock \Timer2:CounterUDB:sC16:counterdp:u0\/co_msb 3.210
Route 1 \Timer2:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Timer2:CounterUDB:sC16:counterdp:u0\/co_msb \Timer2:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell5 U(0,2) 1 \Timer2:CounterUDB:sC16:counterdp:u1\ HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:count_2\/q \FreqDiv_1:count_4\/main_2 3.539
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(1,1) 1 \FreqDiv_1:count_2\ \FreqDiv_1:count_2\/clock_0 \FreqDiv_1:count_2\/q 1.250
Route 1 \FreqDiv_1:count_2\ \FreqDiv_1:count_2\/q \FreqDiv_1:count_4\/main_2 2.289
macrocell12 U(0,1) 1 \FreqDiv_1:count_4\ HOLD 0.000
Clock Skew 0.000
\FreqDiv_2:not_last_reset\/q \FreqDiv_2:count_0\/main_0 3.551
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell26 U(2,1) 1 \FreqDiv_2:not_last_reset\ \FreqDiv_2:not_last_reset\/clock_0 \FreqDiv_2:not_last_reset\/q 1.250
Route 1 \FreqDiv_2:not_last_reset\ \FreqDiv_2:not_last_reset\/q \FreqDiv_2:count_0\/main_0 2.301
macrocell19 U(3,1) 1 \FreqDiv_2:count_0\ HOLD 0.000
Clock Skew 0.000
\Timer1:CounterUDB:disable_run_i\/q \Timer1:CounterUDB:disable_run_i\/main_1 4.039
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell44 U(1,1) 1 \Timer1:CounterUDB:disable_run_i\ \Timer1:CounterUDB:disable_run_i\/clock_0 \Timer1:CounterUDB:disable_run_i\/q 1.250
macrocell44 U(1,1) 1 \Timer1:CounterUDB:disable_run_i\ \Timer1:CounterUDB:disable_run_i\/q \Timer1:CounterUDB:disable_run_i\/main_1 2.789
macrocell44 U(1,1) 1 \Timer1:CounterUDB:disable_run_i\ HOLD 0.000
Clock Skew 0.000
\Timer2:CounterUDB:underflow_reg_i\/q \Timer2:CounterUDB:disable_run_i\/main_3 4.039
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell55 U(0,2) 1 \Timer2:CounterUDB:underflow_reg_i\ \Timer2:CounterUDB:underflow_reg_i\/clock_0 \Timer2:CounterUDB:underflow_reg_i\/q 1.250
Route 1 \Timer2:CounterUDB:underflow_reg_i\ \Timer2:CounterUDB:underflow_reg_i\/q \Timer2:CounterUDB:disable_run_i\/main_3 2.789
macrocell51 U(0,2) 1 \Timer2:CounterUDB:disable_run_i\ HOLD 0.000
Clock Skew 0.000
\Timer2:CounterUDB:disable_run_i\/q \Timer2:CounterUDB:disable_run_i\/main_1 4.060
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell51 U(0,2) 1 \Timer2:CounterUDB:disable_run_i\ \Timer2:CounterUDB:disable_run_i\/clock_0 \Timer2:CounterUDB:disable_run_i\/q 1.250
macrocell51 U(0,2) 1 \Timer2:CounterUDB:disable_run_i\ \Timer2:CounterUDB:disable_run_i\/q \Timer2:CounterUDB:disable_run_i\/main_1 2.810
macrocell51 U(0,2) 1 \Timer2:CounterUDB:disable_run_i\ HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:count_8\/q \FreqDiv_1:count_9\/main_2 4.074
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(0,0) 1 \FreqDiv_1:count_8\ \FreqDiv_1:count_8\/clock_0 \FreqDiv_1:count_8\/q 1.250
Route 1 \FreqDiv_1:count_8\ \FreqDiv_1:count_8\/q \FreqDiv_1:count_9\/main_2 2.824
macrocell17 U(0,0) 1 \FreqDiv_1:count_9\ HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:count_6\/q \FreqDiv_1:count_9\/main_4 4.088
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(1,0) 1 \FreqDiv_1:count_6\ \FreqDiv_1:count_6\/clock_0 \FreqDiv_1:count_6\/q 1.250
Route 1 \FreqDiv_1:count_6\ \FreqDiv_1:count_6\/q \FreqDiv_1:count_9\/main_4 2.838
macrocell17 U(0,0) 1 \FreqDiv_1:count_9\ HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:count_6\/q Net_957/main_5 4.089
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(1,0) 1 \FreqDiv_1:count_6\ \FreqDiv_1:count_6\/clock_0 \FreqDiv_1:count_6\/q 1.250
Route 1 \FreqDiv_1:count_6\ \FreqDiv_1:count_6\/q Net_957/main_5 2.839
macrocell6 U(1,0) 1 Net_957 HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
Net_913/q Net_913/main_3 3.547
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(1,2) 1 Net_913 Net_913/clock_0 Net_913/q 1.250
macrocell5 U(1,2) 1 Net_913 Net_913/q Net_913/main_3 2.297
macrocell5 U(1,2) 1 Net_913 HOLD 0.000
Clock Skew 0.000
\SD_SPIM:BSPIM:mosi_hs_reg\/q \SD_SPIM:BSPIM:mosi_hs_reg\/main_4 3.549
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell32 U(3,4) 1 \SD_SPIM:BSPIM:mosi_hs_reg\ \SD_SPIM:BSPIM:mosi_hs_reg\/clock_0 \SD_SPIM:BSPIM:mosi_hs_reg\/q 1.250
macrocell32 U(3,4) 1 \SD_SPIM:BSPIM:mosi_hs_reg\ \SD_SPIM:BSPIM:mosi_hs_reg\/q \SD_SPIM:BSPIM:mosi_hs_reg\/main_4 2.299
macrocell32 U(3,4) 1 \SD_SPIM:BSPIM:mosi_hs_reg\ HOLD 0.000
Clock Skew 0.000
\SD_SPIM:BSPIM:load_cond\/q \SD_SPIM:BSPIM:load_cond\/main_8 3.558
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell29 U(3,2) 1 \SD_SPIM:BSPIM:load_cond\ \SD_SPIM:BSPIM:load_cond\/clock_0 \SD_SPIM:BSPIM:load_cond\/q 1.250
macrocell29 U(3,2) 1 \SD_SPIM:BSPIM:load_cond\ \SD_SPIM:BSPIM:load_cond\/q \SD_SPIM:BSPIM:load_cond\/main_8 2.308
macrocell29 U(3,2) 1 \SD_SPIM:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
\SD_SPIM:BSPIM:cnt_enable\/q \SD_SPIM:BSPIM:cnt_enable\/main_3 3.876
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell27 U(2,2) 1 \SD_SPIM:BSPIM:cnt_enable\ \SD_SPIM:BSPIM:cnt_enable\/clock_0 \SD_SPIM:BSPIM:cnt_enable\/q 1.250
macrocell27 U(2,2) 1 \SD_SPIM:BSPIM:cnt_enable\ \SD_SPIM:BSPIM:cnt_enable\/q \SD_SPIM:BSPIM:cnt_enable\/main_3 2.626
macrocell27 U(2,2) 1 \SD_SPIM:BSPIM:cnt_enable\ HOLD 0.000
Clock Skew 0.000
\SD_SPIM:BSPIM:state_0\/q \SD_SPIM:BSPIM:cnt_enable\/main_2 4.032
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell37 U(2,2) 1 \SD_SPIM:BSPIM:state_0\ \SD_SPIM:BSPIM:state_0\/clock_0 \SD_SPIM:BSPIM:state_0\/q 1.250
Route 1 \SD_SPIM:BSPIM:state_0\ \SD_SPIM:BSPIM:state_0\/q \SD_SPIM:BSPIM:cnt_enable\/main_2 2.782
macrocell27 U(2,2) 1 \SD_SPIM:BSPIM:cnt_enable\ HOLD 0.000
Clock Skew 0.000
\SD_SPIM:BSPIM:state_0\/q \SD_SPIM:BSPIM:state_2\/main_2 4.032
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell37 U(2,2) 1 \SD_SPIM:BSPIM:state_0\ \SD_SPIM:BSPIM:state_0\/clock_0 \SD_SPIM:BSPIM:state_0\/q 1.250
Route 1 \SD_SPIM:BSPIM:state_0\ \SD_SPIM:BSPIM:state_0\/q \SD_SPIM:BSPIM:state_2\/main_2 2.782
macrocell39 U(2,2) 1 \SD_SPIM:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\SD_SPIM:BSPIM:state_0\/q \SD_SPIM:BSPIM:load_cond\/main_2 4.039
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell37 U(2,2) 1 \SD_SPIM:BSPIM:state_0\ \SD_SPIM:BSPIM:state_0\/clock_0 \SD_SPIM:BSPIM:state_0\/q 1.250
Route 1 \SD_SPIM:BSPIM:state_0\ \SD_SPIM:BSPIM:state_0\/q \SD_SPIM:BSPIM:load_cond\/main_2 2.789
macrocell29 U(3,2) 1 \SD_SPIM:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
\SD_SPIM:BSPIM:ld_ident\/q \SD_SPIM:BSPIM:state_2\/main_9 4.498
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(3,2) 1 \SD_SPIM:BSPIM:ld_ident\ \SD_SPIM:BSPIM:ld_ident\/clock_0 \SD_SPIM:BSPIM:ld_ident\/q 1.250
Route 1 \SD_SPIM:BSPIM:ld_ident\ \SD_SPIM:BSPIM:ld_ident\/q \SD_SPIM:BSPIM:state_2\/main_9 3.248
macrocell39 U(2,2) 1 \SD_SPIM:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\SD_SPIM:BSPIM:cnt_enable\/q \SD_SPIM:BSPIM:BitCounter\/enable 4.647
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell27 U(2,2) 1 \SD_SPIM:BSPIM:cnt_enable\ \SD_SPIM:BSPIM:cnt_enable\/clock_0 \SD_SPIM:BSPIM:cnt_enable\/q 1.250
Route 1 \SD_SPIM:BSPIM:cnt_enable\ \SD_SPIM:BSPIM:cnt_enable\/q \SD_SPIM:BSPIM:BitCounter\/enable 3.397
count7cell U(2,1) 1 \SD_SPIM:BSPIM:BitCounter\ HOLD 0.000
Clock Skew 0.000
\SD_SPIM:BSPIM:ld_ident\/q \SD_SPIM:BSPIM:state_0\/main_9 4.658
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(3,2) 1 \SD_SPIM:BSPIM:ld_ident\ \SD_SPIM:BSPIM:ld_ident\/clock_0 \SD_SPIM:BSPIM:ld_ident\/q 1.250
Route 1 \SD_SPIM:BSPIM:ld_ident\ \SD_SPIM:BSPIM:ld_ident\/q \SD_SPIM:BSPIM:state_0\/main_9 3.408
macrocell37 U(2,2) 1 \SD_SPIM:BSPIM:state_0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:sSTSReg:rstSts:stsreg\/reset 4.634
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(0,2) 1 \Timer2_Reset:Sync:ctrl_reg\ \Timer2_Reset:Sync:ctrl_reg\/busclk \Timer2_Reset:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_928 \Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:sSTSReg:rstSts:stsreg\/reset 2.594
statusicell4 U(0,2) 1 \Timer2:CounterUDB:sSTSReg:rstSts:stsreg\ REMOVAL 0.000
Clock Skew 0.000
\Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:disable_run_i\/main_0 4.662
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(0,2) 1 \Timer2_Reset:Sync:ctrl_reg\ \Timer2_Reset:Sync:ctrl_reg\/busclk \Timer2_Reset:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_928 \Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:disable_run_i\/main_0 2.622
macrocell51 U(0,2) 1 \Timer2:CounterUDB:disable_run_i\ HOLD 0.000
Clock Skew 0.000
\Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:sSTSReg:rstSts:stsreg\/reset 4.826
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(0,1) 1 \Timer1_Reset:Sync:ctrl_reg\ \Timer1_Reset:Sync:ctrl_reg\/busclk \Timer1_Reset:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_917 \Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:sSTSReg:rstSts:stsreg\/reset 2.786
statusicell3 U(0,1) 1 \Timer1:CounterUDB:sSTSReg:rstSts:stsreg\ REMOVAL 0.000
Clock Skew 0.000
\Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:disable_run_i\/main_0 4.851
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(0,1) 1 \Timer1_Reset:Sync:ctrl_reg\ \Timer1_Reset:Sync:ctrl_reg\/busclk \Timer1_Reset:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_917 \Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:disable_run_i\/main_0 2.811
macrocell44 U(1,1) 1 \Timer1:CounterUDB:disable_run_i\ HOLD 0.000
Clock Skew 0.000
\Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:sC16:counterdp:u1\/cs_addr_0 10.785
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(0,2) 1 \Timer2_Reset:Sync:ctrl_reg\ \Timer2_Reset:Sync:ctrl_reg\/busclk \Timer2_Reset:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_928 \Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:reload\/main_0 2.622
macrocell53 U(0,2) 1 \Timer2:CounterUDB:reload\ \Timer2:CounterUDB:reload\/main_0 \Timer2:CounterUDB:reload\/q 3.350
Route 1 \Timer2:CounterUDB:reload\ \Timer2:CounterUDB:reload\/q \Timer2:CounterUDB:sC16:counterdp:u1\/cs_addr_0 2.773
datapathcell5 U(0,2) 1 \Timer2:CounterUDB:sC16:counterdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:sC16:counterdp:u0\/cs_addr_0 10.787
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(0,1) 1 \Timer1_Reset:Sync:ctrl_reg\ \Timer1_Reset:Sync:ctrl_reg\/busclk \Timer1_Reset:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_917 \Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:reload\/main_0 2.811
macrocell46 U(1,1) 1 \Timer1:CounterUDB:reload\ \Timer1:CounterUDB:reload\/main_0 \Timer1:CounterUDB:reload\/q 3.350
Route 1 \Timer1:CounterUDB:reload\ \Timer1:CounterUDB:reload\/q \Timer1:CounterUDB:sC16:counterdp:u0\/cs_addr_0 2.586
datapathcell2 U(1,1) 1 \Timer1:CounterUDB:sC16:counterdp:u0\ HOLD 0.000
Clock Skew 0.000
\Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:sC16:counterdp:u1\/cs_addr_0 10.791
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(0,1) 1 \Timer1_Reset:Sync:ctrl_reg\ \Timer1_Reset:Sync:ctrl_reg\/busclk \Timer1_Reset:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_917 \Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:reload\/main_0 2.811
macrocell46 U(1,1) 1 \Timer1:CounterUDB:reload\ \Timer1:CounterUDB:reload\/main_0 \Timer1:CounterUDB:reload\/q 3.350
Route 1 \Timer1:CounterUDB:reload\ \Timer1:CounterUDB:reload\/q \Timer1:CounterUDB:sC16:counterdp:u1\/cs_addr_0 2.590
datapathcell3 U(0,1) 1 \Timer1:CounterUDB:sC16:counterdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:sC16:counterdp:u0\/cs_addr_0 10.814
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(0,2) 1 \Timer2_Reset:Sync:ctrl_reg\ \Timer2_Reset:Sync:ctrl_reg\/busclk \Timer2_Reset:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_928 \Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:reload\/main_0 2.622
macrocell53 U(0,2) 1 \Timer2:CounterUDB:reload\ \Timer2:CounterUDB:reload\/main_0 \Timer2:CounterUDB:reload\/q 3.350
Route 1 \Timer2:CounterUDB:reload\ \Timer2:CounterUDB:reload\/q \Timer2:CounterUDB:sC16:counterdp:u0\/cs_addr_0 2.802
datapathcell4 U(1,2) 1 \Timer2:CounterUDB:sC16:counterdp:u0\ HOLD 0.000
Clock Skew 0.000
\Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:sC16:counterdp:u1\/ci 20.497
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(0,1) 1 \Timer1_Reset:Sync:ctrl_reg\ \Timer1_Reset:Sync:ctrl_reg\/busclk \Timer1_Reset:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_917 \Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:reload\/main_0 2.811
macrocell46 U(1,1) 1 \Timer1:CounterUDB:reload\ \Timer1:CounterUDB:reload\/main_0 \Timer1:CounterUDB:reload\/q 3.350
Route 1 \Timer1:CounterUDB:reload\ \Timer1:CounterUDB:reload\/q \Timer1:CounterUDB:sC16:counterdp:u0\/cs_addr_0 2.586
datapathcell2 U(1,1) 1 \Timer1:CounterUDB:sC16:counterdp:u0\ \Timer1:CounterUDB:sC16:counterdp:u0\/cs_addr_0 \Timer1:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \Timer1:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Timer1:CounterUDB:sC16:counterdp:u0\/co_msb \Timer1:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell3 U(0,1) 1 \Timer1:CounterUDB:sC16:counterdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:sC16:counterdp:u1\/ci 20.524
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(0,2) 1 \Timer2_Reset:Sync:ctrl_reg\ \Timer2_Reset:Sync:ctrl_reg\/busclk \Timer2_Reset:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_928 \Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:reload\/main_0 2.622
macrocell53 U(0,2) 1 \Timer2:CounterUDB:reload\ \Timer2:CounterUDB:reload\/main_0 \Timer2:CounterUDB:reload\/q 3.350
Route 1 \Timer2:CounterUDB:reload\ \Timer2:CounterUDB:reload\/q \Timer2:CounterUDB:sC16:counterdp:u0\/cs_addr_0 2.802
datapathcell4 U(1,2) 1 \Timer2:CounterUDB:sC16:counterdp:u0\ \Timer2:CounterUDB:sC16:counterdp:u0\/cs_addr_0 \Timer2:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \Timer2:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Timer2:CounterUDB:sC16:counterdp:u0\/co_msb \Timer2:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell5 U(0,2) 1 \Timer2:CounterUDB:sC16:counterdp:u1\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
SD_MISO(0)/fb \SD_SPIM:BSPIM:sR8:Dp:u0\/route_si 8.223
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell7 P12[7] 1 SD_MISO(0) SD_MISO(0)/in_clock SD_MISO(0)/fb 1.743
Route 1 Net_34 SD_MISO(0)/fb \SD_SPIM:BSPIM:sR8:Dp:u0\/route_si 6.480
datapathcell1 U(2,1) 1 \SD_SPIM:BSPIM:sR8:Dp:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_5 7.089
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.828
Route 1 Net_127 Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_5 5.261
macrocell58 U(1,5) 1 \UART_1:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_5 7.089
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.828
Route 1 Net_127 Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_5 5.261
macrocell59 U(1,5) 1 \UART_1:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 8.489
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.828
Route 1 Net_127 Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 6.661
macrocell68 U(0,4) 1 \UART_1:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 8.489
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.828
Route 1 Net_127 Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 6.661
macrocell72 U(0,4) 1 \UART_1:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 9.548
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.828
Route 1 Net_127 Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 7.720
macrocell65 U(2,4) 1 \UART_1:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 10.121
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.828
Route 1 Net_127 Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 8.293
macrocell69 U(0,3) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_6 12.694
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.828
Route 1 Net_127 Rx_1(0)/fb \UART_1:BUART:pollcount_1_split\/main_6 5.231
macrocell60 U(1,5) 1 \UART_1:BUART:pollcount_1_split\ \UART_1:BUART:pollcount_1_split\/main_6 \UART_1:BUART:pollcount_1_split\/q 3.350
Route 1 \UART_1:BUART:pollcount_1_split\ \UART_1:BUART:pollcount_1_split\/q \UART_1:BUART:pollcount_1\/main_6 2.285
macrocell59 U(1,5) 1 \UART_1:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:sRX:RxShifter:u0\/route_si 14.146
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.828
Route 1 Net_127 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_1 6.661
macrocell67 U(0,4) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.307
datapathcell6 U(0,4) 1 \UART_1:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART_1:BUART:rx_status_3\/q \UART_1:BUART:sRX:RxSts\/status_3 2.153
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell72 U(0,4) 1 \UART_1:BUART:rx_status_3\ \UART_1:BUART:rx_status_3\/clock_0 \UART_1:BUART:rx_status_3\/q 1.250
Route 1 \UART_1:BUART:rx_status_3\ \UART_1:BUART:rx_status_3\/q \UART_1:BUART:sRX:RxSts\/status_3 2.903
statusicell5 U(0,3) 1 \UART_1:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\UART_1:BUART:rx_address_detected\/q \UART_1:BUART:rx_state_3\/main_0 3.568
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell61 U(0,5) 1 \UART_1:BUART:rx_address_detected\ \UART_1:BUART:rx_address_detected\/clock_0 \UART_1:BUART:rx_address_detected\/q 1.250
Route 1 \UART_1:BUART:rx_address_detected\ \UART_1:BUART:rx_address_detected\/q \UART_1:BUART:rx_state_3\/main_0 2.318
macrocell70 U(0,5) 1 \UART_1:BUART:rx_state_3\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:rx_bitclk_enable\/q \UART_1:BUART:rx_state_3\/main_2 3.856
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell62 U(0,5) 1 \UART_1:BUART:rx_bitclk_enable\ \UART_1:BUART:rx_bitclk_enable\/clock_0 \UART_1:BUART:rx_bitclk_enable\/q 1.250
Route 1 \UART_1:BUART:rx_bitclk_enable\ \UART_1:BUART:rx_bitclk_enable\/q \UART_1:BUART:rx_state_3\/main_2 2.606
macrocell70 U(0,5) 1 \UART_1:BUART:rx_state_3\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:pollcount_0\/q \UART_1:BUART:pollcount_0\/main_6 3.863
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell58 U(1,5) 1 \UART_1:BUART:pollcount_0\ \UART_1:BUART:pollcount_0\/clock_0 \UART_1:BUART:pollcount_0\/q 1.250
macrocell58 U(1,5) 1 \UART_1:BUART:pollcount_0\ \UART_1:BUART:pollcount_0\/q \UART_1:BUART:pollcount_0\/main_6 2.613
macrocell58 U(1,5) 1 \UART_1:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:rx_state_3\/q \UART_1:BUART:rx_state_3\/main_3 3.871
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell70 U(0,5) 1 \UART_1:BUART:rx_state_3\ \UART_1:BUART:rx_state_3\/clock_0 \UART_1:BUART:rx_state_3\/q 1.250
macrocell70 U(0,5) 1 \UART_1:BUART:rx_state_3\ \UART_1:BUART:rx_state_3\/q \UART_1:BUART:rx_state_3\/main_3 2.621
macrocell70 U(0,5) 1 \UART_1:BUART:rx_state_3\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:txn\/q \UART_1:BUART:txn\/main_0 3.877
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell82 U(1,4) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/clock_0 \UART_1:BUART:txn\/q 1.250
macrocell82 U(1,4) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/q \UART_1:BUART:txn\/main_0 2.627
macrocell82 U(1,4) 1 \UART_1:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:pollcount_1\/q \UART_1:BUART:pollcount_1\/main_4 4.167
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell59 U(1,5) 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/clock_0 \UART_1:BUART:pollcount_1\/q 1.250
macrocell59 U(1,5) 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/q \UART_1:BUART:pollcount_1\/main_4 2.917
macrocell59 U(1,5) 1 \UART_1:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:rx_state_0\/q \UART_1:BUART:sRX:RxShifter:u0\/cs_addr_1 4.199
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell68 U(0,4) 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/clock_0 \UART_1:BUART:rx_state_0\/q 1.250
Route 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/q \UART_1:BUART:sRX:RxShifter:u0\/cs_addr_1 2.949
datapathcell6 U(0,4) 1 \UART_1:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:rx_state_0\/q \UART_1:BUART:rx_count7_bit8_wire\/main_1 4.340
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell68 U(0,4) 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/clock_0 \UART_1:BUART:rx_state_0\/q 1.250
Route 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/q \UART_1:BUART:rx_count7_bit8_wire\/main_1 3.090
macrocell63 U(0,4) 1 \UART_1:BUART:rx_count7_bit8_wire\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:rx_state_0\/q \UART_1:BUART:rx_state_0\/main_1 4.340
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell68 U(0,4) 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/clock_0 \UART_1:BUART:rx_state_0\/q 1.250
macrocell68 U(0,4) 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/q \UART_1:BUART:rx_state_0\/main_1 3.090
macrocell68 U(0,4) 1 \UART_1:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ Clock_3
Source Destination Delay (ns)
\SD_SPIM:BSPIM:state_2\/q SD_MOSI(0)_PAD 38.650
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell39 U(2,2) 1 \SD_SPIM:BSPIM:state_2\ \SD_SPIM:BSPIM:state_2\/clock_0 \SD_SPIM:BSPIM:state_2\/q 1.250
Route 1 \SD_SPIM:BSPIM:state_2\ \SD_SPIM:BSPIM:state_2\/q Net_909/main_0 11.303
macrocell3 U(1,3) 1 Net_909 Net_909/main_0 Net_909/q 3.350
Route 1 Net_909 Net_909/q SD_MOSI(0)/pin_input 7.366
iocell8 P1[7] 1 SD_MOSI(0) SD_MOSI(0)/pin_input SD_MOSI(0)/pad_out 15.381
Route 1 SD_MOSI(0)_PAD SD_MOSI(0)/pad_out SD_MOSI(0)_PAD 0.000
Clock Clock path delay 0.000
Net_911/q SD_SCLK(0)_PAD 24.326
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(1,2) 1 Net_911 Net_911/clock_0 Net_911/q 1.250
Route 1 Net_911 Net_911/q SD_SCLK(0)/pin_input 6.856
iocell9 P12[6] 1 SD_SCLK(0) SD_SCLK(0)/pin_input SD_SCLK(0)/pad_out 16.220
Route 1 SD_SCLK(0)_PAD SD_SCLK(0)/pad_out SD_SCLK(0)_PAD 0.000
Clock Clock path delay 0.000
+ UART_1_IntClock
Source Destination Delay (ns)
\UART_1:BUART:txn\/q Tx_1(0)_PAD 29.490
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell82 U(1,4) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/clock_0 \UART_1:BUART:txn\/q 1.250
Route 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/q Net_126/main_0 3.405
macrocell2 U(0,5) 1 Net_126 Net_126/main_0 Net_126/q 3.350
Route 1 Net_126 Net_126/q Tx_1(0)/pin_input 5.447
iocell10 P12[5] 1 Tx_1(0) Tx_1(0)/pin_input Tx_1(0)/pad_out 16.038
Route 1 Tx_1(0)_PAD Tx_1(0)/pad_out Tx_1(0)_PAD 0.000
Clock Clock path delay 0.000
+ Asynchronous Constraints
+ Recovery
Path Delay Requirement : 30.303ns(33 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
\Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:sSTSReg:rstSts:stsreg\/reset 186.359 MHz 5.366 24.937
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(0,1) 1 \Timer1_Reset:Sync:ctrl_reg\ \Timer1_Reset:Sync:ctrl_reg\/busclk \Timer1_Reset:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_917 \Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:sSTSReg:rstSts:stsreg\/reset 2.786
statusicell3 U(0,1) 1 \Timer1:CounterUDB:sSTSReg:rstSts:stsreg\ RECOVERY -0.000
Clock Skew 0.000
\Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:sSTSReg:rstSts:stsreg\/reset 193.274 MHz 5.174 25.129
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(0,2) 1 \Timer2_Reset:Sync:ctrl_reg\ \Timer2_Reset:Sync:ctrl_reg\/busclk \Timer2_Reset:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_928 \Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:sSTSReg:rstSts:stsreg\/reset 2.594
statusicell4 U(0,2) 1 \Timer2:CounterUDB:sSTSReg:rstSts:stsreg\ RECOVERY -0.000
Clock Skew 0.000
+ Removal
Source Destination Slack (ns) Violation
\Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:sSTSReg:rstSts:stsreg\/reset 4.634
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(0,2) 1 \Timer2_Reset:Sync:ctrl_reg\ \Timer2_Reset:Sync:ctrl_reg\/busclk \Timer2_Reset:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_928 \Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:sSTSReg:rstSts:stsreg\/reset 2.594
statusicell4 U(0,2) 1 \Timer2:CounterUDB:sSTSReg:rstSts:stsreg\ REMOVAL 0.000
Clock Skew 0.000
\Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:sSTSReg:rstSts:stsreg\/reset 4.826
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(0,1) 1 \Timer1_Reset:Sync:ctrl_reg\ \Timer1_Reset:Sync:ctrl_reg\/busclk \Timer1_Reset:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_917 \Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:sSTSReg:rstSts:stsreg\/reset 2.786
statusicell3 U(0,1) 1 \Timer1:CounterUDB:sSTSReg:rstSts:stsreg\ REMOVAL 0.000
Clock Skew 0.000