Static Timing Analysis

Project : APP_FATFS
Build Time : 10/01/14 14:22:16
Device : CY8C5267LTI-LP089
Temperature : -40C - 85/125C
Vdda : 3.30
Vddd : 3.30
Vio0 : 3.30
Vio1 : 3.30
Vio2 : 3.30
Vio3 : 3.30
Voltage : 3.3
Vusb : 3.30
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 100.000 kHz 100.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 33.000 MHz 33.000 MHz N/A
Clock_3 CyMASTER_CLK 1.375 MHz 1.375 MHz 42.542 MHz
Clock_2 CyMASTER_CLK 1.000 MHz 1.000 MHz 27.108 MHz
UART_1_IntClock CyMASTER_CLK 461.538 kHz 464.789 kHz 38.254 MHz
CyBUS_CLK CyMASTER_CLK 33.000 MHz 33.000 MHz 34.642 MHz
CyPLL_OUT CyPLL_OUT 66.000 MHz 66.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 1000ns(1 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
Net_957/q \Timer1:CounterUDB:sC16:counterdp:u1\/ci 27.108 MHz 36.889 963.111
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(2,5) 1 Net_957 Net_957/clock_0 Net_957/q 1.250
Route 1 Net_957 Net_957/q \Timer1:CounterUDB:count_enable\/main_3 9.852
macrocell42 U(1,2) 1 \Timer1:CounterUDB:count_enable\ \Timer1:CounterUDB:count_enable\/main_3 \Timer1:CounterUDB:count_enable\/q 3.350
Route 1 \Timer1:CounterUDB:count_enable\ \Timer1:CounterUDB:count_enable\/q \Timer1:CounterUDB:sC16:counterdp:u0\/cs_addr_1 7.637
datapathcell2 U(2,4) 1 \Timer1:CounterUDB:sC16:counterdp:u0\ \Timer1:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \Timer1:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \Timer1:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Timer1:CounterUDB:sC16:counterdp:u0\/co_msb \Timer1:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell3 U(2,3) 1 \Timer1:CounterUDB:sC16:counterdp:u1\ SETUP 5.090
Clock Skew 0.000
Net_957/q \Timer1:CounterUDB:sC16:counterdp:u0\/cs_addr_1 29.754 MHz 33.609 966.391
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(2,5) 1 Net_957 Net_957/clock_0 Net_957/q 1.250
Route 1 Net_957 Net_957/q \Timer1:CounterUDB:count_enable\/main_3 9.852
macrocell42 U(1,2) 1 \Timer1:CounterUDB:count_enable\ \Timer1:CounterUDB:count_enable\/main_3 \Timer1:CounterUDB:count_enable\/q 3.350
Route 1 \Timer1:CounterUDB:count_enable\ \Timer1:CounterUDB:count_enable\/q \Timer1:CounterUDB:sC16:counterdp:u0\/cs_addr_1 7.637
datapathcell2 U(2,4) 1 \Timer1:CounterUDB:sC16:counterdp:u0\ SETUP 11.520
Clock Skew 0.000
Net_957/q \Timer1:CounterUDB:sC16:counterdp:u1\/cs_addr_1 30.590 MHz 32.690 967.310
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(2,5) 1 Net_957 Net_957/clock_0 Net_957/q 1.250
Route 1 Net_957 Net_957/q \Timer1:CounterUDB:count_enable\/main_3 9.852
macrocell42 U(1,2) 1 \Timer1:CounterUDB:count_enable\ \Timer1:CounterUDB:count_enable\/main_3 \Timer1:CounterUDB:count_enable\/q 3.350
Route 1 \Timer1:CounterUDB:count_enable\ \Timer1:CounterUDB:count_enable\/q \Timer1:CounterUDB:sC16:counterdp:u1\/cs_addr_1 6.718
datapathcell3 U(2,3) 1 \Timer1:CounterUDB:sC16:counterdp:u1\ SETUP 11.520
Clock Skew 0.000
Net_957/q \Timer2:CounterUDB:sC16:counterdp:u1\/ci 31.183 MHz 32.069 967.931
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(2,5) 1 Net_957 Net_957/clock_0 Net_957/q 1.250
Route 1 Net_957 Net_957/q \Timer2:CounterUDB:count_enable\/main_0 9.864
macrocell50 U(1,2) 1 \Timer2:CounterUDB:count_enable\ \Timer2:CounterUDB:count_enable\/main_0 \Timer2:CounterUDB:count_enable\/q 3.350
Route 1 \Timer2:CounterUDB:count_enable\ \Timer2:CounterUDB:count_enable\/q \Timer2:CounterUDB:sC16:counterdp:u0\/cs_addr_1 2.805
datapathcell4 U(1,2) 1 \Timer2:CounterUDB:sC16:counterdp:u0\ \Timer2:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \Timer2:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \Timer2:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Timer2:CounterUDB:sC16:counterdp:u0\/co_msb \Timer2:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell5 U(0,2) 1 \Timer2:CounterUDB:sC16:counterdp:u1\ SETUP 5.090
Clock Skew 0.000
\Timer1:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer1:CounterUDB:sC16:counterdp:u1\/ci 31.303 MHz 31.946 968.054
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(1,0) 1 \Timer1:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer1:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer1:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.580
Route 1 \Timer1:CounterUDB:control_7\ \Timer1:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer1:CounterUDB:count_enable\/main_0 3.579
macrocell42 U(1,2) 1 \Timer1:CounterUDB:count_enable\ \Timer1:CounterUDB:count_enable\/main_0 \Timer1:CounterUDB:count_enable\/q 3.350
Route 1 \Timer1:CounterUDB:count_enable\ \Timer1:CounterUDB:count_enable\/q \Timer1:CounterUDB:sC16:counterdp:u0\/cs_addr_1 7.637
datapathcell2 U(2,4) 1 \Timer1:CounterUDB:sC16:counterdp:u0\ \Timer1:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \Timer1:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \Timer1:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Timer1:CounterUDB:sC16:counterdp:u0\/co_msb \Timer1:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell3 U(2,3) 1 \Timer1:CounterUDB:sC16:counterdp:u1\ SETUP 5.090
Clock Skew 0.000
\Timer1:CounterUDB:sC16:counterdp:u0\/z0 \Timer1:CounterUDB:sC16:counterdp:u1\/ci 31.780 MHz 31.466 968.534
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,4) 1 \Timer1:CounterUDB:sC16:counterdp:u0\ \Timer1:CounterUDB:sC16:counterdp:u0\/clock \Timer1:CounterUDB:sC16:counterdp:u0\/z0 2.320
Route 1 \Timer1:CounterUDB:sC16:counterdp:u0.z0__sig\ \Timer1:CounterUDB:sC16:counterdp:u0\/z0 \Timer1:CounterUDB:sC16:counterdp:u1\/z0i 0.000
datapathcell3 U(2,3) 1 \Timer1:CounterUDB:sC16:counterdp:u1\ \Timer1:CounterUDB:sC16:counterdp:u1\/z0i \Timer1:CounterUDB:sC16:counterdp:u1\/z0_comb 2.960
Route 1 \Timer1:CounterUDB:status_1\ \Timer1:CounterUDB:sC16:counterdp:u1\/z0_comb \Timer1:CounterUDB:reload\/main_1 4.649
macrocell46 U(2,3) 1 \Timer1:CounterUDB:reload\ \Timer1:CounterUDB:reload\/main_1 \Timer1:CounterUDB:reload\/q 3.350
Route 1 \Timer1:CounterUDB:reload\ \Timer1:CounterUDB:reload\/q \Timer1:CounterUDB:sC16:counterdp:u0\/cs_addr_0 3.387
datapathcell2 U(2,4) 1 \Timer1:CounterUDB:sC16:counterdp:u0\ \Timer1:CounterUDB:sC16:counterdp:u0\/cs_addr_0 \Timer1:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \Timer1:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Timer1:CounterUDB:sC16:counterdp:u0\/co_msb \Timer1:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell3 U(2,3) 1 \Timer1:CounterUDB:sC16:counterdp:u1\ SETUP 5.090
Clock Skew 0.000
\Timer2:CounterUDB:sC16:counterdp:u0\/z0 \Timer2:CounterUDB:sC16:counterdp:u1\/ci 33.128 MHz 30.186 969.814
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(1,2) 1 \Timer2:CounterUDB:sC16:counterdp:u0\ \Timer2:CounterUDB:sC16:counterdp:u0\/clock \Timer2:CounterUDB:sC16:counterdp:u0\/z0 2.320
Route 1 \Timer2:CounterUDB:sC16:counterdp:u0.z0__sig\ \Timer2:CounterUDB:sC16:counterdp:u0\/z0 \Timer2:CounterUDB:sC16:counterdp:u1\/z0i 0.000
datapathcell5 U(0,2) 1 \Timer2:CounterUDB:sC16:counterdp:u1\ \Timer2:CounterUDB:sC16:counterdp:u1\/z0i \Timer2:CounterUDB:sC16:counterdp:u1\/z0_comb 2.960
Route 1 \Timer2:CounterUDB:status_1\ \Timer2:CounterUDB:sC16:counterdp:u1\/z0_comb \Timer2:CounterUDB:reload\/main_1 3.954
macrocell53 U(0,2) 1 \Timer2:CounterUDB:reload\ \Timer2:CounterUDB:reload\/main_1 \Timer2:CounterUDB:reload\/q 3.350
Route 1 \Timer2:CounterUDB:reload\ \Timer2:CounterUDB:reload\/q \Timer2:CounterUDB:sC16:counterdp:u0\/cs_addr_0 2.802
datapathcell4 U(1,2) 1 \Timer2:CounterUDB:sC16:counterdp:u0\ \Timer2:CounterUDB:sC16:counterdp:u0\/cs_addr_0 \Timer2:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \Timer2:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Timer2:CounterUDB:sC16:counterdp:u0\/co_msb \Timer2:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell5 U(0,2) 1 \Timer2:CounterUDB:sC16:counterdp:u1\ SETUP 5.090
Clock Skew 0.000
\Timer1:CounterUDB:sC16:counterdp:u1\/z0_comb \Timer1:CounterUDB:sC16:counterdp:u1\/ci 33.293 MHz 30.036 969.964
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(2,3) 1 \Timer1:CounterUDB:sC16:counterdp:u1\ \Timer1:CounterUDB:sC16:counterdp:u1\/clock \Timer1:CounterUDB:sC16:counterdp:u1\/z0_comb 3.850
Route 1 \Timer1:CounterUDB:status_1\ \Timer1:CounterUDB:sC16:counterdp:u1\/z0_comb \Timer1:CounterUDB:reload\/main_1 4.649
macrocell46 U(2,3) 1 \Timer1:CounterUDB:reload\ \Timer1:CounterUDB:reload\/main_1 \Timer1:CounterUDB:reload\/q 3.350
Route 1 \Timer1:CounterUDB:reload\ \Timer1:CounterUDB:reload\/q \Timer1:CounterUDB:sC16:counterdp:u0\/cs_addr_0 3.387
datapathcell2 U(2,4) 1 \Timer1:CounterUDB:sC16:counterdp:u0\ \Timer1:CounterUDB:sC16:counterdp:u0\/cs_addr_0 \Timer1:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \Timer1:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Timer1:CounterUDB:sC16:counterdp:u0\/co_msb \Timer1:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell3 U(2,3) 1 \Timer1:CounterUDB:sC16:counterdp:u1\ SETUP 5.090
Clock Skew 0.000
\Timer1:CounterUDB:count_stored_i\/q \Timer1:CounterUDB:sC16:counterdp:u1\/ci 33.548 MHz 29.808 970.192
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell43 U(1,2) 1 \Timer1:CounterUDB:count_stored_i\ \Timer1:CounterUDB:count_stored_i\/clock_0 \Timer1:CounterUDB:count_stored_i\/q 1.250
Route 1 \Timer1:CounterUDB:count_stored_i\ \Timer1:CounterUDB:count_stored_i\/q \Timer1:CounterUDB:count_enable\/main_2 2.771
macrocell42 U(1,2) 1 \Timer1:CounterUDB:count_enable\ \Timer1:CounterUDB:count_enable\/main_2 \Timer1:CounterUDB:count_enable\/q 3.350
Route 1 \Timer1:CounterUDB:count_enable\ \Timer1:CounterUDB:count_enable\/q \Timer1:CounterUDB:sC16:counterdp:u0\/cs_addr_1 7.637
datapathcell2 U(2,4) 1 \Timer1:CounterUDB:sC16:counterdp:u0\ \Timer1:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \Timer1:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \Timer1:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Timer1:CounterUDB:sC16:counterdp:u0\/co_msb \Timer1:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell3 U(2,3) 1 \Timer1:CounterUDB:sC16:counterdp:u1\ SETUP 5.090
Clock Skew 0.000
\Timer1:CounterUDB:disable_run_i\/q \Timer1:CounterUDB:sC16:counterdp:u1\/ci 34.098 MHz 29.327 970.673
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell44 U(1,2) 1 \Timer1:CounterUDB:disable_run_i\ \Timer1:CounterUDB:disable_run_i\/clock_0 \Timer1:CounterUDB:disable_run_i\/q 1.250
Route 1 \Timer1:CounterUDB:disable_run_i\ \Timer1:CounterUDB:disable_run_i\/q \Timer1:CounterUDB:count_enable\/main_1 2.290
macrocell42 U(1,2) 1 \Timer1:CounterUDB:count_enable\ \Timer1:CounterUDB:count_enable\/main_1 \Timer1:CounterUDB:count_enable\/q 3.350
Route 1 \Timer1:CounterUDB:count_enable\ \Timer1:CounterUDB:count_enable\/q \Timer1:CounterUDB:sC16:counterdp:u0\/cs_addr_1 7.637
datapathcell2 U(2,4) 1 \Timer1:CounterUDB:sC16:counterdp:u0\ \Timer1:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \Timer1:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \Timer1:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Timer1:CounterUDB:sC16:counterdp:u0\/co_msb \Timer1:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell3 U(2,3) 1 \Timer1:CounterUDB:sC16:counterdp:u1\ SETUP 5.090
Clock Skew 0.000
Path Delay Requirement : 727.273ns(1.375 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\SD_SPIM:BSPIM:sR8:Dp:u0\/so_comb \SD_SPIM:BSPIM:mosi_pre_reg\/main_1 42.542 MHz 23.506 703.767
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,0) 1 \SD_SPIM:BSPIM:sR8:Dp:u0\ \SD_SPIM:BSPIM:sR8:Dp:u0\/clock \SD_SPIM:BSPIM:sR8:Dp:u0\/so_comb 8.300
Route 1 \SD_SPIM:BSPIM:mosi_from_dp\ \SD_SPIM:BSPIM:sR8:Dp:u0\/so_comb \SD_SPIM:BSPIM:mosi_pre_reg_split_1\/main_3 5.440
macrocell35 U(2,3) 1 \SD_SPIM:BSPIM:mosi_pre_reg_split_1\ \SD_SPIM:BSPIM:mosi_pre_reg_split_1\/main_3 \SD_SPIM:BSPIM:mosi_pre_reg_split_1\/q 3.350
Route 1 \SD_SPIM:BSPIM:mosi_pre_reg_split_1\ \SD_SPIM:BSPIM:mosi_pre_reg_split_1\/q \SD_SPIM:BSPIM:mosi_pre_reg\/main_1 2.906
macrocell33 U(2,2) 1 \SD_SPIM:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\SD_SPIM:BSPIM:sR8:Dp:u0\/so_comb \SD_SPIM:BSPIM:mosi_pre_reg\/main_0 42.810 MHz 23.359 703.914
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,0) 1 \SD_SPIM:BSPIM:sR8:Dp:u0\ \SD_SPIM:BSPIM:sR8:Dp:u0\/clock \SD_SPIM:BSPIM:sR8:Dp:u0\/so_comb 8.300
Route 1 \SD_SPIM:BSPIM:mosi_from_dp\ \SD_SPIM:BSPIM:sR8:Dp:u0\/so_comb \SD_SPIM:BSPIM:mosi_pre_reg_split\/main_3 5.901
macrocell34 U(2,2) 1 \SD_SPIM:BSPIM:mosi_pre_reg_split\ \SD_SPIM:BSPIM:mosi_pre_reg_split\/main_3 \SD_SPIM:BSPIM:mosi_pre_reg_split\/q 3.350
Route 1 \SD_SPIM:BSPIM:mosi_pre_reg_split\ \SD_SPIM:BSPIM:mosi_pre_reg_split\/q \SD_SPIM:BSPIM:mosi_pre_reg\/main_0 2.298
macrocell33 U(2,2) 1 \SD_SPIM:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\SD_SPIM:BSPIM:sR8:Dp:u0\/so_comb \SD_SPIM:BSPIM:mosi_from_dp_reg\/main_0 51.626 MHz 19.370 707.903
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,0) 1 \SD_SPIM:BSPIM:sR8:Dp:u0\ \SD_SPIM:BSPIM:sR8:Dp:u0\/clock \SD_SPIM:BSPIM:sR8:Dp:u0\/so_comb 8.300
Route 1 \SD_SPIM:BSPIM:mosi_from_dp\ \SD_SPIM:BSPIM:sR8:Dp:u0\/so_comb \SD_SPIM:BSPIM:mosi_from_dp_reg\/main_0 7.560
macrocell31 U(3,4) 1 \SD_SPIM:BSPIM:mosi_from_dp_reg\ SETUP 3.510
Clock Skew 0.000
\SD_SPIM:BSPIM:sR8:Dp:u0\/so_comb \SD_SPIM:BSPIM:mosi_hs_reg\/main_3 51.626 MHz 19.370 707.903
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,0) 1 \SD_SPIM:BSPIM:sR8:Dp:u0\ \SD_SPIM:BSPIM:sR8:Dp:u0\/clock \SD_SPIM:BSPIM:sR8:Dp:u0\/so_comb 8.300
Route 1 \SD_SPIM:BSPIM:mosi_from_dp\ \SD_SPIM:BSPIM:sR8:Dp:u0\/so_comb \SD_SPIM:BSPIM:mosi_hs_reg\/main_3 7.560
macrocell32 U(3,4) 1 \SD_SPIM:BSPIM:mosi_hs_reg\ SETUP 3.510
Clock Skew 0.000
\SD_SPIM:BSPIM:state_2\/q \SD_SPIM:BSPIM:TxStsReg\/status_0 52.890 MHz 18.907 708.366
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell39 U(2,0) 1 \SD_SPIM:BSPIM:state_2\ \SD_SPIM:BSPIM:state_2\/clock_0 \SD_SPIM:BSPIM:state_2\/q 1.250
Route 1 \SD_SPIM:BSPIM:state_2\ \SD_SPIM:BSPIM:state_2\/q \SD_SPIM:BSPIM:tx_status_0\/main_0 7.151
macrocell40 U(2,3) 1 \SD_SPIM:BSPIM:tx_status_0\ \SD_SPIM:BSPIM:tx_status_0\/main_0 \SD_SPIM:BSPIM:tx_status_0\/q 3.350
Route 1 \SD_SPIM:BSPIM:tx_status_0\ \SD_SPIM:BSPIM:tx_status_0\/q \SD_SPIM:BSPIM:TxStsReg\/status_0 5.586
statusicell2 U(2,3) 1 \SD_SPIM:BSPIM:TxStsReg\ SETUP 1.570
Clock Skew 0.000
\SD_SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb \SD_SPIM:BSPIM:RxStsReg\/status_6 54.591 MHz 18.318 708.955
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,0) 1 \SD_SPIM:BSPIM:sR8:Dp:u0\ \SD_SPIM:BSPIM:sR8:Dp:u0\/clock \SD_SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb 5.280
Route 1 \SD_SPIM:BSPIM:rx_status_4\ \SD_SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb \SD_SPIM:BSPIM:rx_status_6\/main_5 2.837
macrocell36 U(2,1) 1 \SD_SPIM:BSPIM:rx_status_6\ \SD_SPIM:BSPIM:rx_status_6\/main_5 \SD_SPIM:BSPIM:rx_status_6\/q 3.350
Route 1 \SD_SPIM:BSPIM:rx_status_6\ \SD_SPIM:BSPIM:rx_status_6\/q \SD_SPIM:BSPIM:RxStsReg\/status_6 5.281
statusicell1 U(3,3) 1 \SD_SPIM:BSPIM:RxStsReg\ SETUP 1.570
Clock Skew 0.000
\SD_SPIM:BSPIM:state_2\/q \SD_SPIM:BSPIM:mosi_pre_reg\/main_1 55.045 MHz 18.167 709.106
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell39 U(2,0) 1 \SD_SPIM:BSPIM:state_2\ \SD_SPIM:BSPIM:state_2\/clock_0 \SD_SPIM:BSPIM:state_2\/q 1.250
Route 1 \SD_SPIM:BSPIM:state_2\ \SD_SPIM:BSPIM:state_2\/q \SD_SPIM:BSPIM:mosi_pre_reg_split_1\/main_0 7.151
macrocell35 U(2,3) 1 \SD_SPIM:BSPIM:mosi_pre_reg_split_1\ \SD_SPIM:BSPIM:mosi_pre_reg_split_1\/main_0 \SD_SPIM:BSPIM:mosi_pre_reg_split_1\/q 3.350
Route 1 \SD_SPIM:BSPIM:mosi_pre_reg_split_1\ \SD_SPIM:BSPIM:mosi_pre_reg_split_1\/q \SD_SPIM:BSPIM:mosi_pre_reg\/main_1 2.906
macrocell33 U(2,2) 1 \SD_SPIM:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\SD_SPIM:BSPIM:BitCounter\/count_4 \SD_SPIM:BSPIM:RxStsReg\/status_6 58.285 MHz 17.157 710.116
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,2) 1 \SD_SPIM:BSPIM:BitCounter\ \SD_SPIM:BSPIM:BitCounter\/clock \SD_SPIM:BSPIM:BitCounter\/count_4 2.110
Route 1 \SD_SPIM:BSPIM:count_4\ \SD_SPIM:BSPIM:BitCounter\/count_4 \SD_SPIM:BSPIM:rx_status_6\/main_0 4.846
macrocell36 U(2,1) 1 \SD_SPIM:BSPIM:rx_status_6\ \SD_SPIM:BSPIM:rx_status_6\/main_0 \SD_SPIM:BSPIM:rx_status_6\/q 3.350
Route 1 \SD_SPIM:BSPIM:rx_status_6\ \SD_SPIM:BSPIM:rx_status_6\/q \SD_SPIM:BSPIM:RxStsReg\/status_6 5.281
statusicell1 U(3,3) 1 \SD_SPIM:BSPIM:RxStsReg\ SETUP 1.570
Clock Skew 0.000
\SD_SPIM:BSPIM:state_1\/q \SD_SPIM:BSPIM:TxStsReg\/status_0 58.648 MHz 17.051 710.222
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell38 U(2,2) 1 \SD_SPIM:BSPIM:state_1\ \SD_SPIM:BSPIM:state_1\/clock_0 \SD_SPIM:BSPIM:state_1\/q 1.250
Route 1 \SD_SPIM:BSPIM:state_1\ \SD_SPIM:BSPIM:state_1\/q \SD_SPIM:BSPIM:tx_status_0\/main_1 5.295
macrocell40 U(2,3) 1 \SD_SPIM:BSPIM:tx_status_0\ \SD_SPIM:BSPIM:tx_status_0\/main_1 \SD_SPIM:BSPIM:tx_status_0\/q 3.350
Route 1 \SD_SPIM:BSPIM:tx_status_0\ \SD_SPIM:BSPIM:tx_status_0\/q \SD_SPIM:BSPIM:TxStsReg\/status_0 5.586
statusicell2 U(2,3) 1 \SD_SPIM:BSPIM:TxStsReg\ SETUP 1.570
Clock Skew 0.000
\SD_SPIM:BSPIM:BitCounter\/count_2 \SD_SPIM:BSPIM:RxStsReg\/status_6 59.913 MHz 16.691 710.582
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,2) 1 \SD_SPIM:BSPIM:BitCounter\ \SD_SPIM:BSPIM:BitCounter\/clock \SD_SPIM:BSPIM:BitCounter\/count_2 2.110
Route 1 \SD_SPIM:BSPIM:count_2\ \SD_SPIM:BSPIM:BitCounter\/count_2 \SD_SPIM:BSPIM:rx_status_6\/main_2 4.380
macrocell36 U(2,1) 1 \SD_SPIM:BSPIM:rx_status_6\ \SD_SPIM:BSPIM:rx_status_6\/main_2 \SD_SPIM:BSPIM:rx_status_6\/q 3.350
Route 1 \SD_SPIM:BSPIM:rx_status_6\ \SD_SPIM:BSPIM:rx_status_6\/q \SD_SPIM:BSPIM:RxStsReg\/status_6 5.281
statusicell1 U(3,3) 1 \SD_SPIM:BSPIM:RxStsReg\ SETUP 1.570
Clock Skew 0.000
Path Delay Requirement : 30.303ns(33 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
\Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:sC16:counterdp:u1\/ci 34.642 MHz 28.867 1.436
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,2) 1 \Timer1_Reset:Sync:ctrl_reg\ \Timer1_Reset:Sync:ctrl_reg\/busclk \Timer1_Reset:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_917 \Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:reload\/main_0 4.750
macrocell46 U(2,3) 1 \Timer1:CounterUDB:reload\ \Timer1:CounterUDB:reload\/main_0 \Timer1:CounterUDB:reload\/q 3.350
Route 1 \Timer1:CounterUDB:reload\ \Timer1:CounterUDB:reload\/q \Timer1:CounterUDB:sC16:counterdp:u0\/cs_addr_0 3.387
datapathcell2 U(2,4) 1 \Timer1:CounterUDB:sC16:counterdp:u0\ \Timer1:CounterUDB:sC16:counterdp:u0\/cs_addr_0 \Timer1:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \Timer1:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Timer1:CounterUDB:sC16:counterdp:u0\/co_msb \Timer1:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell3 U(2,3) 1 \Timer1:CounterUDB:sC16:counterdp:u1\ SETUP 5.090
Clock Skew 0.000
\Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:sC16:counterdp:u1\/ci 37.942 MHz 26.356 3.947
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(0,2) 1 \Timer2_Reset:Sync:ctrl_reg\ \Timer2_Reset:Sync:ctrl_reg\/busclk \Timer2_Reset:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_928 \Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:reload\/main_0 2.824
macrocell53 U(0,2) 1 \Timer2:CounterUDB:reload\ \Timer2:CounterUDB:reload\/main_0 \Timer2:CounterUDB:reload\/q 3.350
Route 1 \Timer2:CounterUDB:reload\ \Timer2:CounterUDB:reload\/q \Timer2:CounterUDB:sC16:counterdp:u0\/cs_addr_0 2.802
datapathcell4 U(1,2) 1 \Timer2:CounterUDB:sC16:counterdp:u0\ \Timer2:CounterUDB:sC16:counterdp:u0\/cs_addr_0 \Timer2:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \Timer2:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Timer2:CounterUDB:sC16:counterdp:u0\/co_msb \Timer2:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell5 U(0,2) 1 \Timer2:CounterUDB:sC16:counterdp:u1\ SETUP 5.090
Clock Skew 0.000
\Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:sC16:counterdp:u0\/cs_addr_0 39.082 MHz 25.587 4.716
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,2) 1 \Timer1_Reset:Sync:ctrl_reg\ \Timer1_Reset:Sync:ctrl_reg\/busclk \Timer1_Reset:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_917 \Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:reload\/main_0 4.750
macrocell46 U(2,3) 1 \Timer1:CounterUDB:reload\ \Timer1:CounterUDB:reload\/main_0 \Timer1:CounterUDB:reload\/q 3.350
Route 1 \Timer1:CounterUDB:reload\ \Timer1:CounterUDB:reload\/q \Timer1:CounterUDB:sC16:counterdp:u0\/cs_addr_0 3.387
datapathcell2 U(2,4) 1 \Timer1:CounterUDB:sC16:counterdp:u0\ SETUP 11.520
Clock Skew 0.000
\Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:sC16:counterdp:u1\/cs_addr_0 40.301 MHz 24.813 5.490
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,2) 1 \Timer1_Reset:Sync:ctrl_reg\ \Timer1_Reset:Sync:ctrl_reg\/busclk \Timer1_Reset:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_917 \Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:reload\/main_0 4.750
macrocell46 U(2,3) 1 \Timer1:CounterUDB:reload\ \Timer1:CounterUDB:reload\/main_0 \Timer1:CounterUDB:reload\/q 3.350
Route 1 \Timer1:CounterUDB:reload\ \Timer1:CounterUDB:reload\/q \Timer1:CounterUDB:sC16:counterdp:u1\/cs_addr_0 2.613
datapathcell3 U(2,3) 1 \Timer1:CounterUDB:sC16:counterdp:u1\ SETUP 11.520
Clock Skew 0.000
\Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:sC16:counterdp:u0\/cs_addr_0 43.335 MHz 23.076 7.227
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(0,2) 1 \Timer2_Reset:Sync:ctrl_reg\ \Timer2_Reset:Sync:ctrl_reg\/busclk \Timer2_Reset:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_928 \Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:reload\/main_0 2.824
macrocell53 U(0,2) 1 \Timer2:CounterUDB:reload\ \Timer2:CounterUDB:reload\/main_0 \Timer2:CounterUDB:reload\/q 3.350
Route 1 \Timer2:CounterUDB:reload\ \Timer2:CounterUDB:reload\/q \Timer2:CounterUDB:sC16:counterdp:u0\/cs_addr_0 2.802
datapathcell4 U(1,2) 1 \Timer2:CounterUDB:sC16:counterdp:u0\ SETUP 11.520
Clock Skew 0.000
\Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:sC16:counterdp:u1\/cs_addr_0 43.390 MHz 23.047 7.256
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(0,2) 1 \Timer2_Reset:Sync:ctrl_reg\ \Timer2_Reset:Sync:ctrl_reg\/busclk \Timer2_Reset:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_928 \Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:reload\/main_0 2.824
macrocell53 U(0,2) 1 \Timer2:CounterUDB:reload\ \Timer2:CounterUDB:reload\/main_0 \Timer2:CounterUDB:reload\/q 3.350
Route 1 \Timer2:CounterUDB:reload\ \Timer2:CounterUDB:reload\/q \Timer2:CounterUDB:sC16:counterdp:u1\/cs_addr_0 2.773
datapathcell5 U(0,2) 1 \Timer2:CounterUDB:sC16:counterdp:u1\ SETUP 11.520
Clock Skew 0.000
\Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:disable_run_i\/main_0 78.266 MHz 12.777 17.526
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,2) 1 \Timer1_Reset:Sync:ctrl_reg\ \Timer1_Reset:Sync:ctrl_reg\/busclk \Timer1_Reset:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_917 \Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:disable_run_i\/main_0 6.687
macrocell44 U(1,2) 1 \Timer1:CounterUDB:disable_run_i\ SETUP 3.510
Clock Skew 0.000
\Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:disable_run_i\/main_0 112.183 MHz 8.914 21.389
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(0,2) 1 \Timer2_Reset:Sync:ctrl_reg\ \Timer2_Reset:Sync:ctrl_reg\/busclk \Timer2_Reset:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_928 \Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:disable_run_i\/main_0 2.824
macrocell51 U(0,2) 1 \Timer2:CounterUDB:disable_run_i\ SETUP 3.510
Clock Skew 0.000
\Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:sSTSReg:rstSts:stsreg\/reset 135.208 MHz 7.396 22.907
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,2) 1 \Timer1_Reset:Sync:ctrl_reg\ \Timer1_Reset:Sync:ctrl_reg\/busclk \Timer1_Reset:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_917 \Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:sSTSReg:rstSts:stsreg\/reset 4.816
statusicell3 U(2,4) 1 \Timer1:CounterUDB:sSTSReg:rstSts:stsreg\ RECOVERY -0.000
Clock Skew 0.000
\Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:sSTSReg:rstSts:stsreg\/reset 186.324 MHz 5.367 24.936
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(0,2) 1 \Timer2_Reset:Sync:ctrl_reg\ \Timer2_Reset:Sync:ctrl_reg\/busclk \Timer2_Reset:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_928 \Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:sSTSReg:rstSts:stsreg\/reset 2.787
statusicell4 U(1,2) 1 \Timer2:CounterUDB:sSTSReg:rstSts:stsreg\ RECOVERY -0.000
Clock Skew 0.000
Path Delay Requirement : 30.303ns(33 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
SD_MISO(0)/fb \SD_SPIM:BSPIM:sR8:Dp:u0\/route_si 69.204 MHz 14.450 15.853
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell7 P12[7] 1 SD_MISO(0) SD_MISO(0)/in_clock SD_MISO(0)/fb 1.743
Route 1 Net_34 SD_MISO(0)/fb \SD_SPIM:BSPIM:sR8:Dp:u0\/route_si 5.927
datapathcell1 U(2,0) 1 \SD_SPIM:BSPIM:sR8:Dp:u0\ SETUP 6.780
Clock Skew 0.000
Path Delay Requirement : 30.303ns(33 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx_1(0)/fb \UART_1:BUART:sRX:RxShifter:u0\/route_si 52.024 MHz 19.222 11.081
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P3[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.685
Route 1 Net_78 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_1 5.666
macrocell65 U(3,1) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.311
datapathcell6 U(3,1) 1 \UART_1:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 78.327 MHz 12.767 17.536
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P3[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.685
Route 1 Net_78 Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 6.572
macrocell58 U(3,2) 1 \UART_1:BUART:pollcount_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 78.327 MHz 12.767 17.536
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P3[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.685
Route 1 Net_78 Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 6.572
macrocell59 U(3,2) 1 \UART_1:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 84.310 MHz 11.861 18.442
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P3[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.685
Route 1 Net_78 Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 5.666
macrocell70 U(3,1) 1 \UART_1:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 89.662 MHz 11.153 19.150
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P3[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.685
Route 1 Net_78 Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 4.958
macrocell63 U(3,0) 1 \UART_1:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 89.662 MHz 11.153 19.150
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P3[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.685
Route 1 Net_78 Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 4.958
macrocell66 U(3,0) 1 \UART_1:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 89.662 MHz 11.153 19.150
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P3[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.685
Route 1 Net_78 Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 4.958
macrocell67 U(3,0) 1 \UART_1:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 2151.52ns(464.789 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART_1:BUART:tx_bitclk\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 38.254 MHz 26.141 2125.374
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell73 U(2,1) 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/clock_0 \UART_1:BUART:tx_bitclk\/q 1.250
Route 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/q \UART_1:BUART:counter_load_not\/main_3 7.787
macrocell57 U(1,0) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_3 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.234
datapathcell8 U(1,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_1:BUART:tx_state_1\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 45.869 MHz 21.801 2129.714
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell76 U(0,0) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 \UART_1:BUART:tx_state_1\/q 1.250
Route 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q \UART_1:BUART:counter_load_not\/main_0 3.447
macrocell57 U(1,0) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_0 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.234
datapathcell8 U(1,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_1:BUART:tx_state_0\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 46.177 MHz 21.656 2129.859
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell75 U(0,0) 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/clock_0 \UART_1:BUART:tx_state_0\/q 1.250
Route 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/q \UART_1:BUART:counter_load_not\/main_1 3.302
macrocell57 U(1,0) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_1 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.234
datapathcell8 U(1,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 47.152 MHz 21.208 2130.307
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell77 U(0,0) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 1.250
Route 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:counter_load_not\/main_2 2.854
macrocell57 U(1,0) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_2 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.234
datapathcell8 U(1,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 47.669 MHz 20.978 2130.537
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell8 U(1,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb 5.680
Route 1 \UART_1:BUART:tx_bitclk_dp\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART_1:BUART:tx_bitclk_enable_pre\/main_0 3.414
macrocell74 U(1,0) 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:tx_bitclk_enable_pre\/main_0 \UART_1:BUART:tx_bitclk_enable_pre\/q 3.350
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:tx_bitclk_enable_pre\/q \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 2.244
datapathcell7 U(0,0) 1 \UART_1:BUART:sTX:TxShifter:u0\ SETUP 6.290
Clock Skew 0.000
\UART_1:BUART:tx_bitclk\/q \UART_1:BUART:sTX:TxSts\/status_0 55.218 MHz 18.110 2133.405
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell73 U(2,1) 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/clock_0 \UART_1:BUART:tx_bitclk\/q 1.250
Route 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/q \UART_1:BUART:tx_status_0\/main_4 8.320
macrocell78 U(0,0) 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/main_4 \UART_1:BUART:tx_status_0\/q 3.350
Route 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/q \UART_1:BUART:sTX:TxSts\/status_0 3.620
statusicell6 U(0,2) 1 \UART_1:BUART:sTX:TxSts\ SETUP 1.570
Clock Skew 0.000
\UART_1:BUART:rx_state_3\/q \UART_1:BUART:sRX:RxBitCounter\/load 57.107 MHz 17.511 2134.004
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell68 U(3,1) 1 \UART_1:BUART:rx_state_3\ \UART_1:BUART:rx_state_3\/clock_0 \UART_1:BUART:rx_state_3\/q 1.250
Route 1 \UART_1:BUART:rx_state_3\ \UART_1:BUART:rx_state_3\/q \UART_1:BUART:rx_counter_load\/main_2 5.824
macrocell62 U(3,0) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_2 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.867
count7cell U(3,1) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 4.220
Clock Skew 0.000
\UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:sTX:TxSts\/status_0 59.126 MHz 16.913 2134.602
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell7 U(0,0) 1 \UART_1:BUART:sTX:TxShifter:u0\ \UART_1:BUART:sTX:TxShifter:u0\/clock \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \UART_1:BUART:tx_fifo_empty\ \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:tx_status_0\/main_2 3.093
macrocell78 U(0,0) 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/main_2 \UART_1:BUART:tx_status_0\/q 3.350
Route 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/q \UART_1:BUART:sTX:TxSts\/status_0 3.620
statusicell6 U(0,2) 1 \UART_1:BUART:sTX:TxSts\ SETUP 1.570
Clock Skew 0.000
\UART_1:BUART:rx_state_0\/q \UART_1:BUART:sRX:RxBitCounter\/load 61.192 MHz 16.342 2135.173
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell66 U(3,0) 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/clock_0 \UART_1:BUART:rx_state_0\/q 1.250
Route 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/q \UART_1:BUART:rx_counter_load\/main_1 4.655
macrocell62 U(3,0) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_1 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.867
count7cell U(3,1) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 4.220
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART_1:BUART:tx_bitclk\/main_0 62.625 MHz 15.968 2135.547
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell8 U(1,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb 5.680
Route 1 \UART_1:BUART:tx_bitclk_dp\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART_1:BUART:tx_bitclk\/main_0 6.778
macrocell73 U(2,1) 1 \UART_1:BUART:tx_bitclk\ SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\Timer1:CounterUDB:sC16:counterdp:u0\/co_msb \Timer1:CounterUDB:sC16:counterdp:u1\/ci 3.210
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,4) 1 \Timer1:CounterUDB:sC16:counterdp:u0\ \Timer1:CounterUDB:sC16:counterdp:u0\/clock \Timer1:CounterUDB:sC16:counterdp:u0\/co_msb 3.210
Route 1 \Timer1:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Timer1:CounterUDB:sC16:counterdp:u0\/co_msb \Timer1:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell3 U(2,3) 1 \Timer1:CounterUDB:sC16:counterdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer2:CounterUDB:sC16:counterdp:u0\/co_msb \Timer2:CounterUDB:sC16:counterdp:u1\/ci 3.210
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(1,2) 1 \Timer2:CounterUDB:sC16:counterdp:u0\ \Timer2:CounterUDB:sC16:counterdp:u0\/clock \Timer2:CounterUDB:sC16:counterdp:u0\/co_msb 3.210
Route 1 \Timer2:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Timer2:CounterUDB:sC16:counterdp:u0\/co_msb \Timer2:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell5 U(0,2) 1 \Timer2:CounterUDB:sC16:counterdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer1:CounterUDB:disable_run_i\/q \Timer1:CounterUDB:disable_run_i\/main_1 3.540
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell44 U(1,2) 1 \Timer1:CounterUDB:disable_run_i\ \Timer1:CounterUDB:disable_run_i\/clock_0 \Timer1:CounterUDB:disable_run_i\/q 1.250
macrocell44 U(1,2) 1 \Timer1:CounterUDB:disable_run_i\ \Timer1:CounterUDB:disable_run_i\/q \Timer1:CounterUDB:disable_run_i\/main_1 2.290
macrocell44 U(1,2) 1 \Timer1:CounterUDB:disable_run_i\ HOLD 0.000
Clock Skew 0.000
\FreqDiv_2:count_0\/q \FreqDiv_2:count_1\/main_1 3.552
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(2,3) 1 \FreqDiv_2:count_0\ \FreqDiv_2:count_0\/clock_0 \FreqDiv_2:count_0\/q 1.250
Route 1 \FreqDiv_2:count_0\ \FreqDiv_2:count_0\/q \FreqDiv_2:count_1\/main_1 2.302
macrocell20 U(2,3) 1 \FreqDiv_2:count_1\ HOLD 0.000
Clock Skew 0.000
\FreqDiv_2:count_3\/q Net_1067/main_5 3.859
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(2,4) 1 \FreqDiv_2:count_3\ \FreqDiv_2:count_3\/clock_0 \FreqDiv_2:count_3\/q 1.250
Route 1 \FreqDiv_2:count_3\ \FreqDiv_2:count_3\/q Net_1067/main_5 2.609
macrocell1 U(2,4) 1 Net_1067 HOLD 0.000
Clock Skew 0.000
\FreqDiv_2:count_3\/q \FreqDiv_2:count_4\/main_1 3.859
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(2,4) 1 \FreqDiv_2:count_3\ \FreqDiv_2:count_3\/clock_0 \FreqDiv_2:count_3\/q 1.250
Route 1 \FreqDiv_2:count_3\ \FreqDiv_2:count_3\/q \FreqDiv_2:count_4\/main_1 2.609
macrocell23 U(2,4) 1 \FreqDiv_2:count_4\ HOLD 0.000
Clock Skew 0.000
\FreqDiv_2:count_3\/q \FreqDiv_2:count_5\/main_4 3.859
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(2,4) 1 \FreqDiv_2:count_3\ \FreqDiv_2:count_3\/clock_0 \FreqDiv_2:count_3\/q 1.250
Route 1 \FreqDiv_2:count_3\ \FreqDiv_2:count_3\/q \FreqDiv_2:count_5\/main_4 2.609
macrocell24 U(2,4) 1 \FreqDiv_2:count_5\ HOLD 0.000
Clock Skew 0.000
\FreqDiv_2:count_3\/q \FreqDiv_2:count_6\/main_4 3.859
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(2,4) 1 \FreqDiv_2:count_3\ \FreqDiv_2:count_3\/clock_0 \FreqDiv_2:count_3\/q 1.250
Route 1 \FreqDiv_2:count_3\ \FreqDiv_2:count_3\/q \FreqDiv_2:count_6\/main_4 2.609
macrocell25 U(2,4) 1 \FreqDiv_2:count_6\ HOLD 0.000
Clock Skew 0.000
\FreqDiv_2:count_3\/q \FreqDiv_2:count_2\/main_4 3.866
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(2,4) 1 \FreqDiv_2:count_3\ \FreqDiv_2:count_3\/clock_0 \FreqDiv_2:count_3\/q 1.250
Route 1 \FreqDiv_2:count_3\ \FreqDiv_2:count_3\/q \FreqDiv_2:count_2\/main_4 2.616
macrocell21 U(2,4) 1 \FreqDiv_2:count_2\ HOLD 0.000
Clock Skew 0.000
\FreqDiv_2:count_2\/q Net_1067/main_6 4.018
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(2,4) 1 \FreqDiv_2:count_2\ \FreqDiv_2:count_2\/clock_0 \FreqDiv_2:count_2\/q 1.250
Route 1 \FreqDiv_2:count_2\ \FreqDiv_2:count_2\/q Net_1067/main_6 2.768
macrocell1 U(2,4) 1 Net_1067 HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\SD_SPIM:BSPIM:load_cond\/q \SD_SPIM:BSPIM:load_cond\/main_8 3.488
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell29 U(2,0) 1 \SD_SPIM:BSPIM:load_cond\ \SD_SPIM:BSPIM:load_cond\/clock_0 \SD_SPIM:BSPIM:load_cond\/q 1.250
macrocell29 U(2,0) 1 \SD_SPIM:BSPIM:load_cond\ \SD_SPIM:BSPIM:load_cond\/q \SD_SPIM:BSPIM:load_cond\/main_8 2.238
macrocell29 U(2,0) 1 \SD_SPIM:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
Net_22/q Net_22/main_3 3.532
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(3,4) 1 Net_22 Net_22/clock_0 Net_22/q 1.250
macrocell2 U(3,4) 1 Net_22 Net_22/q Net_22/main_3 2.282
macrocell2 U(3,4) 1 Net_22 HOLD 0.000
Clock Skew 0.000
\SD_SPIM:BSPIM:ld_ident\/q \SD_SPIM:BSPIM:ld_ident\/main_8 3.538
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(2,3) 1 \SD_SPIM:BSPIM:ld_ident\ \SD_SPIM:BSPIM:ld_ident\/clock_0 \SD_SPIM:BSPIM:ld_ident\/q 1.250
macrocell28 U(2,3) 1 \SD_SPIM:BSPIM:ld_ident\ \SD_SPIM:BSPIM:ld_ident\/q \SD_SPIM:BSPIM:ld_ident\/main_8 2.288
macrocell28 U(2,3) 1 \SD_SPIM:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
\SD_SPIM:BSPIM:mosi_hs_reg\/q \SD_SPIM:BSPIM:mosi_hs_reg\/main_4 3.547
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell32 U(3,4) 1 \SD_SPIM:BSPIM:mosi_hs_reg\ \SD_SPIM:BSPIM:mosi_hs_reg\/clock_0 \SD_SPIM:BSPIM:mosi_hs_reg\/q 1.250
macrocell32 U(3,4) 1 \SD_SPIM:BSPIM:mosi_hs_reg\ \SD_SPIM:BSPIM:mosi_hs_reg\/q \SD_SPIM:BSPIM:mosi_hs_reg\/main_4 2.297
macrocell32 U(3,4) 1 \SD_SPIM:BSPIM:mosi_hs_reg\ HOLD 0.000
Clock Skew 0.000
\SD_SPIM:BSPIM:mosi_from_dp_reg\/q \SD_SPIM:BSPIM:mosi_hs_reg\/main_5 3.549
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell31 U(3,4) 1 \SD_SPIM:BSPIM:mosi_from_dp_reg\ \SD_SPIM:BSPIM:mosi_from_dp_reg\/clock_0 \SD_SPIM:BSPIM:mosi_from_dp_reg\/q 1.250
Route 1 \SD_SPIM:BSPIM:mosi_from_dp_reg\ \SD_SPIM:BSPIM:mosi_from_dp_reg\/q \SD_SPIM:BSPIM:mosi_hs_reg\/main_5 2.299
macrocell32 U(3,4) 1 \SD_SPIM:BSPIM:mosi_hs_reg\ HOLD 0.000
Clock Skew 0.000
\SD_SPIM:BSPIM:cnt_enable\/q \SD_SPIM:BSPIM:cnt_enable\/main_3 3.784
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell27 U(2,0) 1 \SD_SPIM:BSPIM:cnt_enable\ \SD_SPIM:BSPIM:cnt_enable\/clock_0 \SD_SPIM:BSPIM:cnt_enable\/q 1.250
macrocell27 U(2,0) 1 \SD_SPIM:BSPIM:cnt_enable\ \SD_SPIM:BSPIM:cnt_enable\/q \SD_SPIM:BSPIM:cnt_enable\/main_3 2.534
macrocell27 U(2,0) 1 \SD_SPIM:BSPIM:cnt_enable\ HOLD 0.000
Clock Skew 0.000
\SD_SPIM:BSPIM:BitCounter\/count_0 \SD_SPIM:BSPIM:state_0\/main_7 4.553
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,2) 1 \SD_SPIM:BSPIM:BitCounter\ \SD_SPIM:BSPIM:BitCounter\/clock \SD_SPIM:BSPIM:BitCounter\/count_0 1.920
Route 1 \SD_SPIM:BSPIM:count_0\ \SD_SPIM:BSPIM:BitCounter\/count_0 \SD_SPIM:BSPIM:state_0\/main_7 2.633
macrocell37 U(2,2) 1 \SD_SPIM:BSPIM:state_0\ HOLD 0.000
Clock Skew 0.000
\SD_SPIM:BSPIM:BitCounter\/count_0 \SD_SPIM:BSPIM:state_1\/main_7 4.553
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,2) 1 \SD_SPIM:BSPIM:BitCounter\ \SD_SPIM:BSPIM:BitCounter\/clock \SD_SPIM:BSPIM:BitCounter\/count_0 1.920
Route 1 \SD_SPIM:BSPIM:count_0\ \SD_SPIM:BSPIM:BitCounter\/count_0 \SD_SPIM:BSPIM:state_1\/main_7 2.633
macrocell38 U(2,2) 1 \SD_SPIM:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
\SD_SPIM:BSPIM:ld_ident\/q \SD_SPIM:BSPIM:state_0\/main_9 4.623
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(2,3) 1 \SD_SPIM:BSPIM:ld_ident\ \SD_SPIM:BSPIM:ld_ident\/clock_0 \SD_SPIM:BSPIM:ld_ident\/q 1.250
Route 1 \SD_SPIM:BSPIM:ld_ident\ \SD_SPIM:BSPIM:ld_ident\/q \SD_SPIM:BSPIM:state_0\/main_9 3.373
macrocell37 U(2,2) 1 \SD_SPIM:BSPIM:state_0\ HOLD 0.000
Clock Skew 0.000
\SD_SPIM:BSPIM:ld_ident\/q \SD_SPIM:BSPIM:state_1\/main_9 4.623
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(2,3) 1 \SD_SPIM:BSPIM:ld_ident\ \SD_SPIM:BSPIM:ld_ident\/clock_0 \SD_SPIM:BSPIM:ld_ident\/q 1.250
Route 1 \SD_SPIM:BSPIM:ld_ident\ \SD_SPIM:BSPIM:ld_ident\/q \SD_SPIM:BSPIM:state_1\/main_9 3.373
macrocell38 U(2,2) 1 \SD_SPIM:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:sSTSReg:rstSts:stsreg\/reset 4.827
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(0,2) 1 \Timer2_Reset:Sync:ctrl_reg\ \Timer2_Reset:Sync:ctrl_reg\/busclk \Timer2_Reset:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_928 \Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:sSTSReg:rstSts:stsreg\/reset 2.787
statusicell4 U(1,2) 1 \Timer2:CounterUDB:sSTSReg:rstSts:stsreg\ REMOVAL 0.000
Clock Skew 0.000
\Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:disable_run_i\/main_0 4.864
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(0,2) 1 \Timer2_Reset:Sync:ctrl_reg\ \Timer2_Reset:Sync:ctrl_reg\/busclk \Timer2_Reset:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_928 \Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:disable_run_i\/main_0 2.824
macrocell51 U(0,2) 1 \Timer2:CounterUDB:disable_run_i\ HOLD 0.000
Clock Skew 0.000
\Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:sSTSReg:rstSts:stsreg\/reset 6.856
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,2) 1 \Timer1_Reset:Sync:ctrl_reg\ \Timer1_Reset:Sync:ctrl_reg\/busclk \Timer1_Reset:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_917 \Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:sSTSReg:rstSts:stsreg\/reset 4.816
statusicell3 U(2,4) 1 \Timer1:CounterUDB:sSTSReg:rstSts:stsreg\ REMOVAL 0.000
Clock Skew 0.000
\Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:disable_run_i\/main_0 8.727
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,2) 1 \Timer1_Reset:Sync:ctrl_reg\ \Timer1_Reset:Sync:ctrl_reg\/busclk \Timer1_Reset:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_917 \Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:disable_run_i\/main_0 6.687
macrocell44 U(1,2) 1 \Timer1:CounterUDB:disable_run_i\ HOLD 0.000
Clock Skew 0.000
\Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:sC16:counterdp:u1\/cs_addr_0 10.987
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(0,2) 1 \Timer2_Reset:Sync:ctrl_reg\ \Timer2_Reset:Sync:ctrl_reg\/busclk \Timer2_Reset:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_928 \Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:reload\/main_0 2.824
macrocell53 U(0,2) 1 \Timer2:CounterUDB:reload\ \Timer2:CounterUDB:reload\/main_0 \Timer2:CounterUDB:reload\/q 3.350
Route 1 \Timer2:CounterUDB:reload\ \Timer2:CounterUDB:reload\/q \Timer2:CounterUDB:sC16:counterdp:u1\/cs_addr_0 2.773
datapathcell5 U(0,2) 1 \Timer2:CounterUDB:sC16:counterdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:sC16:counterdp:u0\/cs_addr_0 11.016
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(0,2) 1 \Timer2_Reset:Sync:ctrl_reg\ \Timer2_Reset:Sync:ctrl_reg\/busclk \Timer2_Reset:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_928 \Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:reload\/main_0 2.824
macrocell53 U(0,2) 1 \Timer2:CounterUDB:reload\ \Timer2:CounterUDB:reload\/main_0 \Timer2:CounterUDB:reload\/q 3.350
Route 1 \Timer2:CounterUDB:reload\ \Timer2:CounterUDB:reload\/q \Timer2:CounterUDB:sC16:counterdp:u0\/cs_addr_0 2.802
datapathcell4 U(1,2) 1 \Timer2:CounterUDB:sC16:counterdp:u0\ HOLD 0.000
Clock Skew 0.000
\Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:sC16:counterdp:u1\/cs_addr_0 12.753
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,2) 1 \Timer1_Reset:Sync:ctrl_reg\ \Timer1_Reset:Sync:ctrl_reg\/busclk \Timer1_Reset:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_917 \Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:reload\/main_0 4.750
macrocell46 U(2,3) 1 \Timer1:CounterUDB:reload\ \Timer1:CounterUDB:reload\/main_0 \Timer1:CounterUDB:reload\/q 3.350
Route 1 \Timer1:CounterUDB:reload\ \Timer1:CounterUDB:reload\/q \Timer1:CounterUDB:sC16:counterdp:u1\/cs_addr_0 2.613
datapathcell3 U(2,3) 1 \Timer1:CounterUDB:sC16:counterdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:sC16:counterdp:u0\/cs_addr_0 13.527
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,2) 1 \Timer1_Reset:Sync:ctrl_reg\ \Timer1_Reset:Sync:ctrl_reg\/busclk \Timer1_Reset:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_917 \Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:reload\/main_0 4.750
macrocell46 U(2,3) 1 \Timer1:CounterUDB:reload\ \Timer1:CounterUDB:reload\/main_0 \Timer1:CounterUDB:reload\/q 3.350
Route 1 \Timer1:CounterUDB:reload\ \Timer1:CounterUDB:reload\/q \Timer1:CounterUDB:sC16:counterdp:u0\/cs_addr_0 3.387
datapathcell2 U(2,4) 1 \Timer1:CounterUDB:sC16:counterdp:u0\ HOLD 0.000
Clock Skew 0.000
\Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:sC16:counterdp:u1\/ci 20.726
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(0,2) 1 \Timer2_Reset:Sync:ctrl_reg\ \Timer2_Reset:Sync:ctrl_reg\/busclk \Timer2_Reset:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_928 \Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:reload\/main_0 2.824
macrocell53 U(0,2) 1 \Timer2:CounterUDB:reload\ \Timer2:CounterUDB:reload\/main_0 \Timer2:CounterUDB:reload\/q 3.350
Route 1 \Timer2:CounterUDB:reload\ \Timer2:CounterUDB:reload\/q \Timer2:CounterUDB:sC16:counterdp:u0\/cs_addr_0 2.802
datapathcell4 U(1,2) 1 \Timer2:CounterUDB:sC16:counterdp:u0\ \Timer2:CounterUDB:sC16:counterdp:u0\/cs_addr_0 \Timer2:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \Timer2:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Timer2:CounterUDB:sC16:counterdp:u0\/co_msb \Timer2:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell5 U(0,2) 1 \Timer2:CounterUDB:sC16:counterdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:sC16:counterdp:u1\/ci 23.237
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,2) 1 \Timer1_Reset:Sync:ctrl_reg\ \Timer1_Reset:Sync:ctrl_reg\/busclk \Timer1_Reset:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_917 \Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:reload\/main_0 4.750
macrocell46 U(2,3) 1 \Timer1:CounterUDB:reload\ \Timer1:CounterUDB:reload\/main_0 \Timer1:CounterUDB:reload\/q 3.350
Route 1 \Timer1:CounterUDB:reload\ \Timer1:CounterUDB:reload\/q \Timer1:CounterUDB:sC16:counterdp:u0\/cs_addr_0 3.387
datapathcell2 U(2,4) 1 \Timer1:CounterUDB:sC16:counterdp:u0\ \Timer1:CounterUDB:sC16:counterdp:u0\/cs_addr_0 \Timer1:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \Timer1:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Timer1:CounterUDB:sC16:counterdp:u0\/co_msb \Timer1:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell3 U(2,3) 1 \Timer1:CounterUDB:sC16:counterdp:u1\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
SD_MISO(0)/fb \SD_SPIM:BSPIM:sR8:Dp:u0\/route_si 7.670
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell7 P12[7] 1 SD_MISO(0) SD_MISO(0)/in_clock SD_MISO(0)/fb 1.743
Route 1 Net_34 SD_MISO(0)/fb \SD_SPIM:BSPIM:sR8:Dp:u0\/route_si 5.927
datapathcell1 U(2,0) 1 \SD_SPIM:BSPIM:sR8:Dp:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 7.643
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P3[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.685
Route 1 Net_78 Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 4.958
macrocell63 U(3,0) 1 \UART_1:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 7.643
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P3[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.685
Route 1 Net_78 Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 4.958
macrocell66 U(3,0) 1 \UART_1:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 7.643
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P3[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.685
Route 1 Net_78 Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 4.958
macrocell67 U(3,0) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 8.351
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P3[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.685
Route 1 Net_78 Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 5.666
macrocell70 U(3,1) 1 \UART_1:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 9.257
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P3[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.685
Route 1 Net_78 Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 6.572
macrocell58 U(3,2) 1 \UART_1:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 9.257
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P3[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.685
Route 1 Net_78 Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 6.572
macrocell59 U(3,2) 1 \UART_1:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:sRX:RxShifter:u0\/route_si 14.012
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P3[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.685
Route 1 Net_78 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_1 5.666
macrocell65 U(3,1) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.311
datapathcell6 U(3,1) 1 \UART_1:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART_1:BUART:rx_status_3\/q \UART_1:BUART:sRX:RxSts\/status_3 2.174
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell70 U(3,1) 1 \UART_1:BUART:rx_status_3\ \UART_1:BUART:rx_status_3\/clock_0 \UART_1:BUART:rx_status_3\/q 1.250
Route 1 \UART_1:BUART:rx_status_3\ \UART_1:BUART:rx_status_3\/q \UART_1:BUART:sRX:RxSts\/status_3 2.924
statusicell5 U(3,2) 1 \UART_1:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\UART_1:BUART:rx_last\/q \UART_1:BUART:rx_state_2\/main_9 3.495
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell63 U(3,0) 1 \UART_1:BUART:rx_last\ \UART_1:BUART:rx_last\/clock_0 \UART_1:BUART:rx_last\/q 1.250
Route 1 \UART_1:BUART:rx_last\ \UART_1:BUART:rx_last\/q \UART_1:BUART:rx_state_2\/main_9 2.245
macrocell67 U(3,0) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:pollcount_1\/q \UART_1:BUART:pollcount_1\/main_2 3.561
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell59 U(3,2) 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/clock_0 \UART_1:BUART:pollcount_1\/q 1.250
macrocell59 U(3,2) 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/q \UART_1:BUART:pollcount_1\/main_2 2.311
macrocell59 U(3,2) 1 \UART_1:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:rx_load_fifo\/q \UART_1:BUART:sRX:RxShifter:u0\/f0_load 3.564
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell64 U(3,1) 1 \UART_1:BUART:rx_load_fifo\ \UART_1:BUART:rx_load_fifo\/clock_0 \UART_1:BUART:rx_load_fifo\/q 1.250
Route 1 \UART_1:BUART:rx_load_fifo\ \UART_1:BUART:rx_load_fifo\/q \UART_1:BUART:sRX:RxShifter:u0\/f0_load 2.314
datapathcell6 U(3,1) 1 \UART_1:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:txn\/q \UART_1:BUART:txn\/main_0 3.776
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell80 U(1,0) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/clock_0 \UART_1:BUART:txn\/q 1.250
macrocell80 U(1,0) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/q \UART_1:BUART:txn\/main_0 2.526
macrocell80 U(1,0) 1 \UART_1:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:pollcount_0\/q \UART_1:BUART:pollcount_0\/main_3 3.871
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell58 U(3,2) 1 \UART_1:BUART:pollcount_0\ \UART_1:BUART:pollcount_0\/clock_0 \UART_1:BUART:pollcount_0\/q 1.250
macrocell58 U(3,2) 1 \UART_1:BUART:pollcount_0\ \UART_1:BUART:pollcount_0\/q \UART_1:BUART:pollcount_0\/main_3 2.621
macrocell58 U(3,2) 1 \UART_1:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:pollcount_0\/q \UART_1:BUART:pollcount_1\/main_4 3.871
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell58 U(3,2) 1 \UART_1:BUART:pollcount_0\ \UART_1:BUART:pollcount_0\/clock_0 \UART_1:BUART:pollcount_0\/q 1.250
Route 1 \UART_1:BUART:pollcount_0\ \UART_1:BUART:pollcount_0\/q \UART_1:BUART:pollcount_1\/main_4 2.621
macrocell59 U(3,2) 1 \UART_1:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:txn\/main_4 4.104
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell77 U(0,0) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 1.250
Route 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:txn\/main_4 2.854
macrocell80 U(1,0) 1 \UART_1:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:tx_state_0\/main_3 4.107
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell77 U(0,0) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 1.250
Route 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:tx_state_0\/main_3 2.857
macrocell75 U(0,0) 1 \UART_1:BUART:tx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:tx_state_1\/main_2 4.107
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell77 U(0,0) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 1.250
Route 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:tx_state_1\/main_2 2.857
macrocell76 U(0,0) 1 \UART_1:BUART:tx_state_1\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ Clock_3
Source Destination Delay (ns)
\SD_SPIM:BSPIM:state_2\/q SD_MOSI(0)_PAD 35.351
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell39 U(2,0) 1 \SD_SPIM:BSPIM:state_2\ \SD_SPIM:BSPIM:state_2\/clock_0 \SD_SPIM:BSPIM:state_2\/q 1.250
Route 1 \SD_SPIM:BSPIM:state_2\ \SD_SPIM:BSPIM:state_2\/q Net_909/main_0 7.166
macrocell4 U(3,3) 1 Net_909 Net_909/main_0 Net_909/q 3.350
Route 1 Net_909 Net_909/q SD_MOSI(0)/pin_input 8.204
iocell8 P1[7] 1 SD_MOSI(0) SD_MOSI(0)/pin_input SD_MOSI(0)/pad_out 15.381
Route 1 SD_MOSI(0)_PAD SD_MOSI(0)/pad_out SD_MOSI(0)_PAD 0.000
Clock Clock path delay 0.000
Net_911/q SD_SCLK(0)_PAD 23.991
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(1,0) 1 Net_911 Net_911/clock_0 Net_911/q 1.250
Route 1 Net_911 Net_911/q SD_SCLK(0)/pin_input 6.521
iocell9 P12[6] 1 SD_SCLK(0) SD_SCLK(0)/pin_input SD_SCLK(0)/pad_out 16.220
Route 1 SD_SCLK(0)_PAD SD_SCLK(0)/pad_out SD_SCLK(0)_PAD 0.000
Clock Clock path delay 0.000
+ UART_1_IntClock
Source Destination Delay (ns)
\UART_1:BUART:txn\/q Tx_1(0)_PAD 29.236
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell80 U(1,0) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/clock_0 \UART_1:BUART:txn\/q 1.250
Route 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/q Net_73/main_0 2.525
macrocell3 U(1,0) 1 Net_73 Net_73/main_0 Net_73/q 3.350
Route 1 Net_73 Net_73/q Tx_1(0)/pin_input 7.132
iocell10 P3[1] 1 Tx_1(0) Tx_1(0)/pin_input Tx_1(0)/pad_out 14.979
Route 1 Tx_1(0)_PAD Tx_1(0)/pad_out Tx_1(0)_PAD 0.000
Clock Clock path delay 0.000
+ Asynchronous Constraints
+ Recovery
Path Delay Requirement : 30.303ns(33 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
\Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:sSTSReg:rstSts:stsreg\/reset 135.208 MHz 7.396 22.907
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,2) 1 \Timer1_Reset:Sync:ctrl_reg\ \Timer1_Reset:Sync:ctrl_reg\/busclk \Timer1_Reset:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_917 \Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:sSTSReg:rstSts:stsreg\/reset 4.816
statusicell3 U(2,4) 1 \Timer1:CounterUDB:sSTSReg:rstSts:stsreg\ RECOVERY -0.000
Clock Skew 0.000
\Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:sSTSReg:rstSts:stsreg\/reset 186.324 MHz 5.367 24.936
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(0,2) 1 \Timer2_Reset:Sync:ctrl_reg\ \Timer2_Reset:Sync:ctrl_reg\/busclk \Timer2_Reset:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_928 \Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:sSTSReg:rstSts:stsreg\/reset 2.787
statusicell4 U(1,2) 1 \Timer2:CounterUDB:sSTSReg:rstSts:stsreg\ RECOVERY -0.000
Clock Skew 0.000
+ Removal
Source Destination Slack (ns) Violation
\Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:sSTSReg:rstSts:stsreg\/reset 4.827
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(0,2) 1 \Timer2_Reset:Sync:ctrl_reg\ \Timer2_Reset:Sync:ctrl_reg\/busclk \Timer2_Reset:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_928 \Timer2_Reset:Sync:ctrl_reg\/control_0 \Timer2:CounterUDB:sSTSReg:rstSts:stsreg\/reset 2.787
statusicell4 U(1,2) 1 \Timer2:CounterUDB:sSTSReg:rstSts:stsreg\ REMOVAL 0.000
Clock Skew 0.000
\Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:sSTSReg:rstSts:stsreg\/reset 6.856
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,2) 1 \Timer1_Reset:Sync:ctrl_reg\ \Timer1_Reset:Sync:ctrl_reg\/busclk \Timer1_Reset:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_917 \Timer1_Reset:Sync:ctrl_reg\/control_0 \Timer1:CounterUDB:sSTSReg:rstSts:stsreg\/reset 4.816
statusicell3 U(2,4) 1 \Timer1:CounterUDB:sSTSReg:rstSts:stsreg\ REMOVAL 0.000
Clock Skew 0.000