Static Timing Analysis

Project : APP_Sample
Build Time : 09/29/14 22:33:52
Device : CY8C5267LTI-LP089
Temperature : -40C - 85/125C
Vdda : 3.30
Vddd : 3.30
Vio0 : 3.30
Vio1 : 3.30
Vio2 : 3.30
Vio3 : 3.30
Voltage : 3.3
Vusb : 3.30
Expand All | Collapse All | Show All Paths | Hide All Paths
+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
Clock_1(routed) Clock_1(routed) 2.000  Hz 2.000  Hz N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 48.000 MHz 48.000 MHz N/A
Clock_1 CyMASTER_CLK 2.000  Hz 2.000  Hz N/A
CyBUS_CLK CyMASTER_CLK 48.000 MHz 48.000 MHz N/A
CyPLL_OUT CyPLL_OUT 48.000 MHz 48.000 MHz N/A
+ Clock To Output Section
+ Clock_1(routed)
Source Destination Delay (ns)
ClockBlock/dclk_0 LED2(0)_PAD 31.039
Type Location Fanout Instance/Net Source Dest Delay (ns)
clockblockcell F(Clock,0) 1 ClockBlock Input Delay ClockBlock/dclk_0 0.000
Route 1 Net_3_local ClockBlock/dclk_0 Net_4/main_0 6.342
macrocell1 U(3,0) 1 Net_4 Net_4/main_0 Net_4/q 3.350
Route 1 Net_4 Net_4/q LED2(0)/pin_input 5.414
iocell2 P12[1] 1 LED2(0) LED2(0)/pin_input LED2(0)/pad_out 15.933
Route 1 LED2(0)_PAD LED2(0)/pad_out LED2(0)_PAD 0.000
Clock Clock path delay 0.000
ClockBlock/dclk_0 LED2(0)_PAD 31.039
Type Location Fanout Instance/Net Source Dest Delay (ns)
clockblockcell F(Clock,0) 1 ClockBlock Input Delay ClockBlock/dclk_0 0.000
Route 1 Net_3_local ClockBlock/dclk_0 Net_4/main_0 6.342
macrocell1 U(3,0) 1 Net_4 Net_4/main_0 Net_4/q 3.350
Route 1 Net_4 Net_4/q LED2(0)/pin_input 5.414
iocell2 P12[1] 1 LED2(0) LED2(0)/pin_input LED2(0)/pad_out 15.933
Route 1 LED2(0)_PAD LED2(0)/pad_out LED2(0)_PAD 0.000
Clock Clock path delay 0.000
ClockBlock/dclk_0 LED1(0)_PAD 19.268
Type Location Fanout Instance/Net Source Dest Delay (ns)
clockblockcell F(Clock,0) 1 ClockBlock Input Delay ClockBlock/dclk_0 0.000
Route 1 Net_3_local ClockBlock/dclk_0 LED1(0)/pin_input 3.413
iocell1 P12[0] 1 LED1(0) LED1(0)/pin_input LED1(0)/pad_out 15.855
Route 1 LED1(0)_PAD LED1(0)/pad_out LED1(0)_PAD 0.000
Clock Clock path delay 0.000
ClockBlock/dclk_0 LED1(0)_PAD 19.268
Type Location Fanout Instance/Net Source Dest Delay (ns)
clockblockcell F(Clock,0) 1 ClockBlock Input Delay ClockBlock/dclk_0 0.000
Route 1 Net_3_local ClockBlock/dclk_0 LED1(0)/pin_input 3.413
iocell1 P12[0] 1 LED1(0) LED1(0)/pin_input LED1(0)/pad_out 15.855
Route 1 LED1(0)_PAD LED1(0)/pad_out LED1(0)_PAD 0.000
Clock Clock path delay 0.000